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參數(shù)資料
| 型號(hào)： | XC5210-5PC84I |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列（FPGA） |
| 文件頁數(shù)： | 5/73頁 |
| 文件大?。?/td> | 598K |
| 代理商： | XC5210-5PC84I |
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R
November 5, 1998 (Version 5.2)
7-87
XC5200 Series Field Programmable Gate Arrays
7
single-length lines, double-length lines, and Longlines all
routed through the GRM. The direct connects, LIM, and
logic-cell
feedthrough
are
Versa-Block. Throughout the XC5200 interconnect, an effi-
cient multiplexing scheme, in combination with three layer
metal (TLM), was used to improve the overall efficiency of
silicon usage.
contained
within
each
Performance Overview
The XC5200 family has been benchmarked with many
designs running synchronous clock rates beyond 66 MHz.
The performance of any design depends on the circuit to be
implemented, and the delay through the combinatorial and
sequential logic elements, plus the delay in the intercon-
nect routing. A rough estimate of timing can be made by
assuming 3-6 ns per logic level, which includes direct-con-
nect routing delays, depending on speed grade. More
accurate estimations can be made using the information in
the Switching Characteristic Guideline section.
Taking Advantage of Reconfiguration
FPGA devices can be reconfigured to change logic function
while resident in the system. This capability gives the sys-
tem designer a new degree of freedom not available with
any other type of logic.
Hardware can be changed as easily as software. Design
updates or modifications are easy, and can be made to
products already in the field. An FPGA can even be recon-
figured dynamically to perform different functions at differ-
ent times.
Reconfigurable logic can be used to implement system
self-diagnostics, create systems capable of being reconfig-
ured for different environments or operations, or implement
multi-purpose hardware for a given application. As an
added benefit, using reconfigurable FPGA devices simpli-
fies hardware design and debugging and shortens product
time-to-market.
Detailed Functional Description
Configurable Logic Blocks (CLBs)
Figure 4
shows the logic in the XC5200 CLB, which con-
sists of four Logic Cells (LC[3:0]). Each Logic Cell consists
of an independent 4-input Lookup Table (LUT), and a
D-Type flip-flop or latch with common clock, clock enable,
and clear, but individually selectable clock polarity. Addi-
tional logic features provided in the CLB are:
An independent 5-input LUT by combining two 4-input
LUTs.
High-speed carry propagate logic.
High-speed pattern decoding.
High-speed direct connection to flip-flop D-inputs.
Individual selection of either a transparent,
level-sensitive latch or a D flip-flop.
Four 3-state buffers with a shared Output Enable.
5-Input Functions
Figure 5
illustrates how the outputs from the LUTs from
LC0 and LC1 can be combined with a 2:1 multiplexer
(F5_MUX) to provide a 5-input function. The outputs from
the LUTs of LC2 and LC3 can be similarly combined.
Figure 5: Two LUTs in Parallel Combined to Create a
5-input Function
out
Q
Qout
DO
Q
D
FD
X
FD
CO
DI
X
CLR
LC0
CK
CE
5-Input Function
D
DO
F5_MUX
DI
F
F4
F3
F2
F1
F4
F3
F2
F1
I1
I2
I3
I4
I5
CI
F
LC1
X5710
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