參數(shù)資料
型號： XC5210-5PC84I
英文描述： Field Programmable Gate Array (FPGA)
中文描述： 現(xiàn)場可編程門陣列（FPGA）
文件頁數(shù)： 71/73頁
文件大小： 598K
代理商： XC5210-5PC84I
R
November 5, 1998 (Version 5.2)
7-153
XC5200 Series Field Programmable Gate Arrays
7
Additional No Connect (N.C.) Connections for HQ208 and HQ240 Packages
Notes:
* Pins labeled VCC* are internally bonded to a VCC plane within the BG225 and BG352 packages. The external pins for the
BG225 are: B2, D8, H15, R8, B14, R1, H1, and R15. The external pins for the BG352 are: A10, A17, B2, B25, D13, D19, D7,
G23, H4, K1, K26, N23, P4, U1, U26, W23, Y4, AC14, AC20, AC8, AE2, AE25, AF10, and AF17.
Pins labeled GND* are internally bonded to a ground plane within the BG225 and BG352 packages. The external pins for the
BG225 are: A1, D12, G7, G9, H6, H8, H10, J8, K8, A8, F8, G8, H2, H7, H9, J7, J9, M8. The external pins for the BG352 are:
A1, A2, A5, A8, A14, A19, A22, A25, A26, B1, B26, E1, E26, H1, H26, N1, P26, W1, W26, AB1, AB26, AE1, AE26, AF1,
AF13, AF19, AF2, AF22, AF25, AF26, AF5, AF8.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 1056 = BSCAN.UPD
235.
236.
237.
238.
239.
240.
241.
242.
243.
244.
I/O
I/O
I/O (A4)
I/O (A5)
I/O
I/O
I/O
I/O
I/O (A6)
I/O (A7)
GND
-
-
-
-
-
-
M5
P1
N1
M3
M2
L5
M1
L4
L3
L2
L1
-
-
B11
A11
D12
C12
B12
A12
C13
B13
A13
B14
GND*
90
93
99
102
105
111
114
117
126
129
-
134
135
-
136
137
138
139
140
141
174
175
176
177
178
179
180
181
182
202
203
205
206
207
208
209
210
211
A10
D9
C9
B9
A9
E9
C8
B8
GND*
HQ208
HQ240
219
22
37
83
98
143
158
204
-
206
207
208
1
3
51
52
53
54
102
104
105
107
155
156
157
158
-
Pin
Description
PQ160
HQ208
HQ240
PG299
BG225
BG352
Boundary Scan Order
相關(guān)PDF資料
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XC5210-6PQ160I Field Programmable Gate Array (FPGA)
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