參數(shù)資料
型號(hào): XC5210-5PC84I
英文描述: Field Programmable Gate Array (FPGA)
中文描述: 現(xiàn)場(chǎng)可編程門陣列(FPGA)
文件頁數(shù): 51/73頁
文件大小: 598K
代理商: XC5210-5PC84I
R
November 5, 1998 (Version 5.2)
7-133
XC5200 Series Field Programmable Gate Arrays
7
Device-Specific Pinout Tables
Device-specific tables include all packages for each XC5200-Series device. They follow the pad locations around the die,
and include boundary scan register locations.
Pin Locations for XC5202 Devices
The following table may contain pinout information for unsupported device/package combinations. Please see the
availability charts elsewhere in the XC5200 Series data sheet for availability information.
Pin
Description
VCC
I/O (A8)
I/O (A9)
I/O
I/O
I/O (A10)
I/O (A11)
GND
I/O (A12)
I/O (A13)
I/O (A14)
I/O (A15)
VCC
GND
GCK1 (A16, I/O)
I/O (A17)
I/O (TDI)
I/O (TCK)
GND
I/O (TMS)
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
M1 (I/O)
GND
M0 (I/O)
VCC
M2 (I/O)
GCK2 (I/O)
VQ64*
-
57
58
-
-
-
59
-
60
61
62
63
64
-
1
2
3
4
-
5
6
-
-
-
7
8
9
-
10
PC84
2
3
4
-
-
5
6
-
7
8
9
10
11
12
13
14
15
16
-
17
18
-
-
19
20
21
22
23
24
-
-
25
26
-
27
-
28
29
30
31
32
33
34
35
PQ100
92
93
94
95
96
97
98
-
99
100
1
2
3
4
5
6
7
8
-
9
10
-
11
12
13
14
15
16
17
18
-
19
20
-
21
22
23
24
25
26
27
28
29
30
VQ100
89
90
91
92
93
94
95
-
96
97
98
99
100
1
2
3
4
5
-
6
7
-
8
9
10
11
12
13
14
15
-
16
17
-
18
19
20
21
22
23
24
25
26
27
TQ144
128
129
130
131
132
133
134
137
138
139
142
143
144
1
2
3
6
7
8
11
12
13
14
15
16
17
18
19
20
21
22
23
24
27
28
29
32
33
34
35
36
37
38
39
PG156
H3
H1
G1
G2
G3
F1
F2
F3
E3
C1
B1
B2
C3
C4
B3
A1
B4
A3
C6
A5
C7
B7
A6
A7
A8
C8
B8
C9
B9
A9
B10
C10
A10
C11
B12
A13
B13
B14
A15
C13
A16
C14
B15
B16
Boundary Scan Order
-
51
54
57
63
66
69
-
78
81
90
93
-
-
102
105
111
114
-
117
123
126
129
135
138
-
-
141
147
150
153
159
162
-
165
171
174
177
186
-
189
-
192
195
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
-
11
27.
28.
29.
30.
31.
12
13
14
15
-
16
-
17
18
32.
33.
34.
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