- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4169 > XC5210-6PQ240C (Xilinx Inc)IC FPGA 324 CLB'S 240-PQFP PDF資料下載
參數(shù)資料
| 型號： | XC5210-6PQ240C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 22/73頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 324 CLB'S 240-PQFP |
| 產(chǎn)品變化通告： | XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010 |
| 標準包裝： | 24 |
| 系列： | XC5200 |
| LAB/CLB數(shù)： | 324 |
| 邏輯元件/單元數(shù)： | 1296 |
| 輸入/輸出數(shù)： | 196 |
| 門數(shù)： | 16000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 240-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 240-PQFP（32x32） |
| 其它名稱： | 122-1151 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當(dāng)前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁
R
November 5, 1998 (Version 5.2)
7-111
XC5200 Series Field Programmable Gate Arrays
7
When the UCLK_SYNC option is enabled, the user can
externally hold the open-drain DONE output Low, and thus
stall all further progress in the start-up sequence until
DONE is released and has gone High. This option can be
used to force synchronization of several FPGAs to a com-
mon user clock, or to guarantee that all devices are suc-
cessfully configured before any I/Os go active.
If either of these two options is selected, and no user clock
is specified in the design or attached to the device, the chip
could reach a point where the configuration of the device is
complete and the Done pin is asserted, but the outputs do
not become active. The solution is either to recreate the
bitstream specifying the start-up clock as CCLK, or to sup-
ply the appropriate user clock.
Start-up Sequence
The Start-up sequence begins when the configuration
memory is full, and the total number of configuration clocks
received since INIT went High equals the loaded value of
the length count.
The next rising clock edge sets a flip-flop Q0, shown in
Figure 26. Q0 is the leading bit of a 5-bit shift register. The
outputs of this register can be programmed to control three
events.
The release of the open-drain DONE output
The change of configuration-related pins to the user
function, activating all IOBs.
The termination of the global Set/Reset initialization of
all CLB and IOB storage elements.
The DONE pin can also be wire-ANDed with DONE pins of
other FPGAs or with other external signals, and can then
be used as input to bit Q3 of the start-up register. This is
called “Start-up Timing Synchronous to Done In” and is
selected by either CCLK_SYNC or UCLK_SYNC.
When DONE is not used as an input, the operation is called
“Start-up Timing Not Synchronous to DONE In,” and is
selected by either CCLK_NOSYNC or UCLK_NOSYNC.
As a configuration option, the start-up control register
beyond Q0 can be clocked either by subsequent CCLK
pulses or from an on-chip user net called STARTUP.CLK.
These signals can be accessed by placing the STARTUP
library symbol.
Start-up from CCLK
If CCLK is used to drive the start-up, Q0 through Q3 pro-
vide the timing. Heavy lines in Figure 25 show the default
timing, which is compatible with XC2000 and XC3000
devices using early DONE and late Reset. The thin lines
indicate all other possible timing options.
Start-up from a User Clock (STARTUP.CLK)
When, instead of CCLK, a user-supplied start-up clock is
selected, Q1 is used to bridge the unknown phase relation-
ship between CCLK and the user clock. This arbitration
causes an unavoidable one-cycle uncertainty in the timing
of the rest of the start-up sequence.
DONE Goes High to Signal End of Configuration
In
all
configuration
modes
except
Express
mode,
XC5200-Series devices read the expected length count
from the bitstream and store it in an internal register. The
length count varies according to the number of devices and
the composition of the daisy chain.
Each device also
counts the number of CCLKs during configuration.
Two conditions have to be met in order for the DONE pin to
go high:
the chip's internal memory must be full, and
the configuration length count must be met,
exactly.
This is important because the counter that determines
when the length count is met begins with the very first
CCLK, not the first one after the preamble.
Therefore, if a stray bit is inserted before the preamble, or
the data source is not ready at the time of the first CCLK,
the internal counter that holds the number of CCLKs will be
one ahead of the actual number of data bits read. At the
end of configuration, the configuration memory will be full,
but the number of bits in the internal counter will not match
the expected length count.
As a consequence, a Master mode device will continue to
send out CCLKs until the internal counter turns over to
zero, and then reaches the correct length count a second
time. This will take several seconds [224
CCLK period]
— which is sometimes interpreted as the device not config-
uring at all.
If it is not possible to have the data ready at the time of the
first CCLK, the problem can be avoided by increasing the
number in the length count by the appropriate value.
In Express mode, there is no length count. The DONE pin
for each device goes High when the device has received its
quota of configuration data. Wiring the DONE pins of sev-
eral devices together delays start-up of all devices until all
are fully configured.
Note that DONE is an open-drain output and does not go
High unless an internal pull-up is activated or an external
pull-up is attached. The internal pull-up is activated as the
default by the bitstream generation software.
Release of User I/O After DONE Goes High
By default, the user I/O are released one CCLK cycle after
the DONE pin goes High. If CCLK is not clocked after
DONE goes High, the outputs remain in their initial state —
3-stated, with a 20 k
- 100 k pull-up. The delay from
Product Obsolete or Under Obsolescence
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC5210-5PQ240C | IC FPGA 324 CLB'S 240-PQFP |
| XC5210-6PQ208C | IC FPGA 324 CLB'S 208-PQFP |
| 88997-2 | CONTACT TIN SOLDER FLAT FLEX |
| ABC65DREI-S93 | CONN EDGECARD 130PS .100 EYELET |
| GMC22DTEF | CONN EDGECARD 44POS .100 EYELET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC5210-6PQ240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| XC5210-6PQG208C | 制造商:Xilinx 功能描述: |
| XC52106T144C | 制造商:Xilinx 功能描述: |
| XC5210-6TQ144C | 功能描述:IC FPGA 324 CLB'S 144-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC5200 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XC5210-6TQ144I | 制造商:Xilinx 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。