參數(shù)資料
型號(hào)： XC56L307VF160
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 24/104頁(yè)
文件大?。?/td> 0K
描述： IC DSP 24BIT FIXED POINT 196-BGA
標(biāo)準(zhǔn)包裝： 126
系列： DSP563xx
類型： 定點(diǎn)
接口： 主機(jī)接口，SSI，SCI
時(shí)鐘速率： 160MHz
非易失內(nèi)存： ROM（576 B）
芯片上RAM： 576kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.80V
安裝類型： 表面貼裝
封裝/外殼： 196-LBGA
供應(yīng)商設(shè)備封裝： 196-MAPBGA（15x15）
包裝： 托盤
DSP56L307 Technical Data, Rev. 6
2-6
Freescale Semiconductor
Specifications
2.4.3
Phase Lock Loop (PLL) Characteristics
Table 2-5.
Clock Operation
No.
Characteristics
Symbol
100 MHz
160 MHz
Min
Max
Min
Max
1
Frequency of EXTAL (EXTAL Pin Frequency)
The rise and fall time of this external clock should be 3 ns maximum.
Ef
0100.0
0160.0
2
EXTAL input high1, 2
With PLL disabled (46.7%–53.3% duty cycle
6)
With PLL enabled (42.5%–57.5% duty cycle6)
ETH
4.67 ns
4.25 ns
∞
157.0
s
2.92 ns
2.66 ns
∞
157.0
s
3
EXTAL input low1, 2
With PLL disabled (46.7%–53.3% duty cycle
6)
With PLL enabled (42.5%–57.5% duty cycle6)
ETL
4.67 ns
4.25 ns
∞
157.0
s
2.92 ns
2.66 ns
∞
157.0
s
4
EXTAL cycle time
2
With PLL disabled
With PLL enabled
ETC
10.00 ns
∞
273.1
s
6.25 ns
∞
273.1
s
5
Internal clock change from EXTAL fall with PLL disabled
4.3 ns
11.0 ns
4.3 ns
11.0 ns
6
a.Internal clock rising edge from EXTAL rising edge with PLL enabled
(MF = 1 or 2 or 4, PDF = 1, Ef > 15 MHz)
3,5
b. Internal clock falling edge from EXTAL falling edge with PLL
enabled (MF
≤4, PDF ≠ 1, Ef / PDF > 15 MHz)3,5
0.0 ns
1.8 ns
0.0 ns
1.8 ns
7
Instruction cycle time = ICYC = TC
4
(see Figure 2-4) (46.7%–53.3% duty cycle)
With PLL disabled
With PLL enabled
ICYC
20.0 ns
10.00 ns
∞
8.53
s
13.5 ns
6.25 ns
∞
8.53
s
Notes:
1.
Measured at 50 percent of the input transition.
2.
The maximum value for PLL enabled is given for minimum VCO frequency (see Table 2-4) and maximum MF.
3.
Periodically sampled and not 100 percent tested.
4.
The maximum value for PLL enabled is given for minimum VCO frequency and maximum DF.
5.
The skew is not guaranteed for any other MF value.
6.
The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time
required for correction operation, however, remains the same at lower operating frequencies; therefore, when a lower clock
frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time
requirements are met.
Table 2-6.
PLL Characteristics
Characteristics
100 MHz
160 MHz
Unit
Min
Max
Min
Max
Voltage Controlled Oscillator (VCO) frequency when
PLL enabled (MF
× Ef × 2/PDF)
30
20030320
MHz
PLL external capacitor (PCAP pin to VCCP) (CPCAP
1)
@ MF
≤4
@ MF > 4
(580
× MF) 100
830
× MF
(780
× MF) 140
1470
× MF
(580
× MF) 100
830
× MF
(780
× MF) 140
1470
× MF
pF
Note:
CPCAP is the value of the PLL capacitor (connected between the PCAP pin and VCCP) computed using the appropriate expression
listed above.
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