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| 型號： | XC56L307VF160 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 94/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 24BIT FIXED POINT 196-BGA |
| 標(biāo)準(zhǔn)包裝： | 126 |
| 系列： | DSP563xx |
| 類型： | 定點(diǎn) |
| 接口： | 主機(jī)接口，SSI，SCI |
| 時(shí)鐘速率： | 160MHz |
| 非易失內(nèi)存： | ROM（576 B） |
| 芯片上RAM： | 576kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.80V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
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External Memory Expansion Port (Port A)
DSP56L307 Technical Data, Rev. 6
Freescale Semiconductor
1-5
1.5.2
External Data Bus
1.5.3
External Bus Control
Table 1-6.
External Data Bus Signals
Signal Name
Type
State During
Reset
State During
Stop or Wait
Signal Description
D[0–23]
Input/ Output
Ignored Input
Last state:
Input: Ignored
Output:
Last value
Data Bus—When the DSP is the bus master, D[0–23] are
active-high, bidirectional input/outputs that provide the
bidirectional data bus for external program and data
memory accesses. Otherwise, D[0–23] drivers are tri-
stated. If the last state is output, these lines have weak
keepers that maintain the last output state even when all
drivers are tri-stated.
Table 1-7.
External Bus Control Signals
Signal Name
Type
State During
Reset, Stop, or
Wait
Signal Description
AA[0–3]
Output
Tri-stated
Address Attribute—When defined as AA, these signals can be used as chip
selects or additional address lines. The default use defines a priority scheme
under which only one AA signal can be asserted at a time. Setting the AA priority
disable (APD) bit (Bit 14) of the Operating Mode Register, the priority
mechanism is disabled and the lines can be used together as four external lines
that can be decoded externally into 16 chip select signals.
RD
Output
Tri-stated
Read Enable—When the DSP is the bus master, RD is an active-low output that
is asserted to read external memory on the data bus (D[0–23]). Otherwise, RD is
tri-stated.
WR
Output
Tri-stated
Write Enable—When the DSP is the bus master, WR is an active-low output
that is asserted to write external memory on the data bus (D[0–23]). Otherwise,
the signals are tri-stated.
TA
Input
Ignored Input
Transfer Acknowledge—If the DSP56L307 is the bus master and there is no
external bus activity, or the DSP56L307 is not the bus master, the TA input is
ignored. The TA input is a data transfer acknowledge (DTACK) function that can
extend an external bus cycle indefinitely. Any number of wait states (1,
2. . .infinity) can be added to the wait states inserted by the bus control register
(BCR) by keeping TA deasserted. In typical operation, TA is deasserted at the
start of a bus cycle, is asserted to enable completion of the bus cycle, and is
deasserted before the next bus cycle. The current bus cycle completes one
clock period after TA is asserted synchronous to CLKOUT. The number of wait
states is determined by the TA input or by the BCR, whichever is longer. The
BCR can be used to set the minimum number of wait states in external bus
cycles.
To use the TA functionality, the BCR must be programmed to at least one wait
state. A zero wait state access cannot be extended by TA deassertion;
otherwise, improper operation may result.
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