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參數資料
型號: XC56L307VF160
廠商: Freescale Semiconductor
文件頁數: 62/104頁
文件大小: 0K
描述: IC DSP 24BIT FIXED POINT 196-BGA
標準包裝: 126
系列: DSP563xx
類型: 定點
接口: 主機接口,SSI,SCI
時鐘速率: 160MHz
非易失內存: ROM(576 B)
芯片上RAM: 576kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.80V
安裝類型: 表面貼裝
封裝/外殼: 196-LBGA
供應商設備封裝: 196-MAPBGA(15x15)
包裝: 托盤
DSP56L307 Technical Data, Rev. 6
2-40
Freescale Semiconductor
Specifications
Table 2-20.
ESSI Timings at 160 MHz
No.
Characteristics1,2,3
Symbol
Expression
Min
Max
Condi-
tion4
Unit
430
Clock cycle
5
tSSICC
8
× TC
6
× T
C
50.0
37.5
i ck
x ck
ns
431
Clock high period
For internal clock
For external clock
4
× TC 10.0
3
× T
C
15.0
18.8
ns
432
Clock low period
For internal clock
For external clock
4
× TC 10.0
3
× T
C
15.0
18.8
ns
433
RXC rising edge to FSR out (bl) high
37.0
22.0
x ck
i ck a
ns
434
RXC rising edge to FSR out (bl) low
37.0
22.0
x ck
i ck a
ns
435
RXC rising edge to FSR out (wr) high
6
39.0
24.0
x ck
i ck a
ns
436
RXC rising edge to FSR out (wr) low6
39.0
24.0
x ck
i ck a
ns
437
RXC rising edge to FSR out (wl) high
36.0
21.0
x ck
i ck a
ns
438
RXC rising edge to FSR out (wl) low
37.0
22.0
x ck
i ck a
ns
439
Data in set-up time before RXC (SCK in Synchronous mode)
falling edge
0.0
19.0
x ck
i ck
ns
440
Data in hold time after RXC falling edge
5.0
3.0
x ck
i ck
ns
441
FSR input (bl, wr) high before RXC falling edge
6
1.0
6.0
x ck
i ck a
ns
442
FSR input (wl) high before RXC falling edge
1.0
6.0
x ck
i ck a
ns
443
FSR input hold time after RXC falling edge
3.0
0.0
x ck
i ck a
ns
444
Flags input set-up before RXC falling edge
0.0
19.0
x ck
i ck s
ns
445
Flags input hold time after RXC falling edge
6.0
0.0
x ck
i ck s
ns
446
TXC rising edge to FST out (bl) high
29.0
15.0
x ck
i ck
ns
447
TXC rising edge to FST out (bl) low
31.0
17.0
x ck
i ck
ns
448
TXC rising edge to FST out (wr) high6
31.0
17.0
x ck
i ck
ns
449
TXC rising edge to FST out (wr) low6
33.0
19.0
x ck
i ck
ns
450
TXC rising edge to FST out (wl) high
30.0
16.0
x ck
i ck
ns
451
TXC rising edge to FST out (wl) low
31.0
17.0
x ck
i ck
ns
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