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參數(shù)資料
型號(hào): XC56L307VF160
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 87/104頁(yè)
文件大小: 0K
描述: IC DSP 24BIT FIXED POINT 196-BGA
標(biāo)準(zhǔn)包裝: 126
系列: DSP563xx
類(lèi)型: 定點(diǎn)
接口: 主機(jī)接口,SSI,SCI
時(shí)鐘速率: 160MHz
非易失內(nèi)存: ROM(576 B)
芯片上RAM: 576kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.80V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 196-LBGA
供應(yīng)商設(shè)備封裝: 196-MAPBGA(15x15)
包裝: 托盤(pán)
Input (EXTAL) Jitter Requirements
DSP56L307 Technical Data, Rev. 6
Freescale Semiconductor
4-5
4.4.2
Phase Jitter Performance
The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL and CLKOUT
for a given device in specific temperature, voltage, input frequency, MF, and capacitive load on CLKOUT. These
variations are a result of the PLL locking mechanism. For input frequencies greater than 15 MHz and MF
≤4, this
jitter is less than
±0.6 ns; otherwise, this jitter is not guaranteed. However, for MF < 10 and input frequencies
greater than 10 MHz, this jitter is less than
±2 ns.
4.4.3
Frequency Jitter Performance
The frequency jitter of the PLL is defined as the variation of the frequency of CLKOUT. For small MF (MF < 10)
this jitter is smaller than 0.5 percent. For mid-range MF (10 < MF < 500) this jitter is between 0.5 percent and
approximately 2 percent. For large MF (MF > 500), the frequency jitter is 2–3 percent.
4.5 Input (EXTAL) Jitter Requirements
The allowed jitter on the frequency of EXTAL is 0.5 percent. If the rate of change of the frequency of EXTAL is slow
(that is, it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is
fast (that is, it does not stay at an extreme value for a long time), then the allowed jitter can be 2 percent. The phase
and frequency jitter performance results are valid only if the input jitter is less than the prescribed values.
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