參數(shù)資料
型號: XC5VLX220-2FF1760I
廠商: Xilinx Inc
文件頁數(shù): 42/91頁
文件大?。?/td> 0K
描述: IC FPGA VIRTEX-5 220K 1760FBGA
標(biāo)準包裝: 1
系列: Virtex®-5 LX
LAB/CLB數(shù): 17280
邏輯元件/單元數(shù): 221184
RAM 位總計: 7077888
輸入/輸出數(shù): 800
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 1760-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1760-FCBGA
配用: 568-5088-ND - BOARD DEMO DAC1408D750
HW-AFX-FF1760-500-G-ND - BOARD DEV VIRTEX 5 FF1760
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
47
Block RAM and FIFO Switching Characteristics
Table 68: Block RAM and FIFO Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-2
-1
Block RAM and FIFO Clock to Out Delays
TRCKO_DO and TRCKO_DOR(1)
Clock CLK to DOUT output (without output
register)(2,3)
1.79
1.92
2.19
ns, Max
Clock CLK to DOUT output (with output register)(4,5)
0.61
0.69
0.82
ns, Max
Clock CLK to DOUT output with ECC (without output
register)(2,3)
2.64
3.03
3.61
ns, Max
Clock CLK to DOUT output with ECC (with output
register)(4,5)
0.66
0.77
0.93
ns, Max
Clock CLK to DOUT output with Cascade (without
output register)(2)
2.10
2.44
2.94
ns, Max
Clock CLK to DOUT output with Cascade (with output
register)(4)
0.91
1.07
1.30
ns, Max
TRCKO_FLAGS
Clock CLK to FIFO flags outputs(6)
0.76
0.87
1.02
ns, Max
TRCKO_POINTERS
Clock CLK to FIFO pointer outputs(7)
1.10
1.26
1.48
ns, Max
TRCKO_ECCR
Clock CLK to BITERR (with output register)
0.66
0.77
0.93
ns, Max
TRCKO_ECC
Clock CLK to BITERR (without output register)
2.48
2.85
3.41
ns, Max
Clock CLK to ECCPARITY in standard ECC mode
1.29
1.47
1.74
ns, Max
Clock CLK to ECCPARITY in ECC encode only mode
0.77
0.89
1.05
ns, Max
Setup and Hold Times Before/After Clock CLK
TRCCK_ADDR/TRCKC_ADDR
ADDR inputs(8)
0.34
0.30
0.40
0.32
0.48
0.36
ns, Min
TRDCK_DI/TRCKD_DI
DIN inputs(9)
0.27
0.28
0.30
0.28
0.35
0.29
ns, Min
TRDCK_DI_ECC/TRCKD_DI_ECC
DIN inputs with ECC in standard mode(9)
0.33
0.32
0.37
0.33
0.42
0.36
ns, Min
DIN inputs with ECC encode only(9
0.68
0.32
0.72
0.33
0.77
0.36
ns, Min
TRCCK_EN/TRCKC_EN
Block RAM Enable (EN) input
0.32
0.15
0.36
0.15
0.42
0.15
ns, Min
TRCCK_REGCE/TRCKC_REGCE
CE input of output register
0.15
0.22
0.16
0.24
0.18
0.27
ns, Min
TRCCK_SSR/TRCKC_SSR
Synchronous Set/ Reset (SSR) input
0.17
0.23
0.21
0.25
0.26
0.28
ns, Min
TRCCK_WE/TRCKC_WE
Write Enable (WE) input
0.44
0.16
0.51
0.17
0.63
0.18
ns, Min
TRCCK_WREN/TRCKC_WREN
WREN/RDEN FIFO inputs(10)
0.36
0.30
0.41
0.34
0.48
0.40
ns, Min
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