參數(shù)資料
型號: XC5VLX220-2FF1760I
廠商: Xilinx Inc
文件頁數(shù): 46/91頁
文件大?。?/td> 0K
描述: IC FPGA VIRTEX-5 220K 1760FBGA
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-5 LX
LAB/CLB數(shù): 17280
邏輯元件/單元數(shù): 221184
RAM 位總計(jì): 7077888
輸入/輸出數(shù): 800
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 1760-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1760-FCBGA
配用: 568-5088-ND - BOARD DEMO DAC1408D750
HW-AFX-FF1760-500-G-ND - BOARD DEV VIRTEX 5 FF1760
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
50
TDSPDO_{PCINPCOUT, CRYCINPCOUT,
MULTSIGNINPCOUT, PCINCRYCOUT,
CRYCINCRYCOUT, MULTSIGNINCRYCOUT,
PCINMULTSIGNOUT, CRYCINMULTSIGNOUT,
MULTSIGNINMULTSIGNOUT}
{PCIN, CARRYCASCIN, MULTSIGNIN}
input to {PCOUT, CARRYCASCOUT,
MULTSIGNOUT} output
1.43
1.60
2.02
ns
Clock to Outs from Output Register Clock to Output Pins
TDSPCKO_{PP, CRYOUTP}
CLK (PREG) to {P, CARRYOUT} output
0.45
0.48
0.56
ns
TDSPCKO_{CRYCOUTP, PCOUTP, MULTSIGNOUTP}
CLK (PREG) to {CARRYCASCOUT,
PCOUT, MULTSIGNOUT} output
0.48
0.53
0.62
ns
Clock to Outs from Pipeline Register Clock to Output Pins
TDSPCKO_{PM, CRYOUTM}
CLK (MREG) to {P, CARRYOUT} output
1.81
2.10
2.47
ns
TDSPCKO_{PCOUTM, CRYCOUTM,
MULTSIGNOUTM}
CLK (MREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output
1.91
2.13
2.66
ns
Clock to Outs from Input Register Clock to Output Pins
TDSPCKO_{PA, CRYOUTA, PB, CRYOUTB}_M
CLK (AREG, BREG) to {P, CARRYOUT}
output using multiplier
3.09
3.57
4.23
ns
TDSPCKO_{PA, CRYOUTA, PB, CRYOUTB}_NM
CLK (AREG, BREG) to {P, CARRYOUT}
output not using multiplier
1.90
2.11
2.63
ns
TDSPCKO_{PC, CRYOUTC}
CLK (CREG) to {P, CARRYOUT} output
1.89
2.11
2.62
ns
Clock to Outs from Input Register Clock to Cascading Output Pins
TDSPCKO_{ACOUTA, BCOUTB}
CLK (AREG, BREG) to {ACOUT,
BCOUT}
0.61
0.68
0.79
ns
TDSPCKO_{PCOUTA, CRYCOUTA, MULTSIGNOUTA,
PCOUTB, CRYCOUTB, MULTSIGNOUTB}_M
CLK (AREG, BREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output using multiplier
3.09
3.57
4.23
ns
TDSPCKO_{PCOUTA, CRYCOUTA, MULTSIGNOUTA,
PCOUTB, CRYCOUTB, MULTSIGNOUTB}_NM
CLK (AREG, BREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output not using multiplier
2.03
2.27
2.82
ns
TDSPCKO_{PCOUTC, CRYCOUTC, MULTSIGNOUTC}
CLK (CREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
output
2.03
2.26
2.82
ns
Maximum Frequency
FMAX
With all registers used
550
500
450
MHz
FMAX_PATDET
With pattern detector
515
465
410
MHz
FMAX_MULT_NOMREG
Two register multiply without MREG
374
324
275
MHz
FMAX_MULT_NOMREG_PATDET
Two register multiply without MREG with
pattern detect
345
300
254
MHz
Table 69: DSP48E Switching Characteristics (Cont’d)
Symbol
Description
Speed
Units
-3
-2
-1
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