參數資料
型號: XC6VCX130T-1FFG1156I
廠商: Xilinx Inc
文件頁數: 11/52頁
文件大?。?/td> 0K
描述: IC FPGA VIRTEX 6 128K 1156FFGBGA
產品培訓模塊: Virtex-6 FPGA Overview
產品變化通告: Virtex-6 FIFO Input Logic Reset 18/Apr/2011
標準包裝: 1
系列: Virtex® 6 CXT
LAB/CLB數: 10000
邏輯元件/單元數: 128000
RAM 位總計: 9732096
輸入/輸出數: 600
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 1156-BBGA,FCBGA
供應商設備封裝: 1156-FCBGA(35x35)
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
19
GTX Transceiver DC Input and Output Levels
Table 25 summarizes the DC output specifications of the GTX transceivers in Virtex-6 CXT FPGAs. Consult the Virtex-6
FPGA GTX Transceivers User Guide for further details.
Table 25: GTX Transceiver DC Specifications
Symbol
DC Parameter
Conditions
Min
Typ
Max
Units
DVPPIN
Differential peak-to-peak input
voltage
External AC coupled
125
2000
mV
VIN
Absolute input voltage
DC coupled
MGTAVTT = 1.2V
–400
MGTAVTT
mV
VCMIN
Common mode input voltage
DC coupled
MGTAVTT = 1.2V
2/3 MGTAVTT
mV
DVPPOUT
Differential peak-to-peak output
voltage(1)
Transmitter output swing is set to
maximum setting
1000
mV
VCMOUTDC
DC common mode output voltage Equation based
MGTAVTT – DVPPOUT/4
mV
RIN
Differential input resistance
80
100
130
ROUT
Differential output resistance
80
100
120
TOSKEW
Transmitter output pair (TXP and TXN) intra-pair skew
2
8
ps
CEXT
Recommended external AC coupling capacitor(2)
100
nF
Notes:
1.
The output swing and preemphasis levels are programmable using the attributes discussed in Virtex-6 FPGA GTX Transceivers User Guide
and can result in values lower than reported in this table.
2.
Other values can be used as appropriate to conform to specific protocols and standards.
X-Ref Target - Figure 11
Figure 11: Single-Ended Peak-to-Peak Voltage
X-Ref Target - Figure 12
Figure 12: Differential Peak-to-Peak Voltage
0
+V
P
N
ds153_11_041410
Single-Ended
Voltage
0
+V
–V
P–N
ds153_12_041410
Differential
Voltage
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