參數(shù)資料
型號: XC6VCX130T-1FFG1156I
廠商: Xilinx Inc
文件頁數(shù): 39/52頁
文件大小: 0K
描述: IC FPGA VIRTEX 6 128K 1156FFGBGA
產(chǎn)品培訓(xùn)模塊: Virtex-6 FPGA Overview
產(chǎn)品變化通告: Virtex-6 FIFO Input Logic Reset 18/Apr/2011
標(biāo)準(zhǔn)包裝: 1
系列: Virtex® 6 CXT
LAB/CLB數(shù): 10000
邏輯元件/單元數(shù): 128000
RAM 位總計(jì): 9732096
輸入/輸出數(shù): 600
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 1156-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1156-FCBGA(35x35)
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
44
Clock Buffers and Networks
Table 53: Global Clock Switching Characteristics (Including BUFGCTRL)
Symbol
Description
Speed Grade
Units
-2
-1
TBCCCK_CE/TBCCKC_CE(1)
CE pins Setup/Hold
0.16/0.00
ns
TBCCCK_S/TBCCKC_S(1)
S pins Setup/Hold
0.16/0.00
ns
TBCCKO_O(2)
BUFGCTRL delay from I0/I1 to O
0.10
ns
Maximum Frequency
FMAX
Global clock tree (BUFG)
700
MHz
Notes:
1.
TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
parameters do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold
times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching
between clocks.
2.
TBGCKO_O (BUFG delay from I0 to O) values are the same as TBCCKO_O values.
Table 54: Input/Output Clock Switching Characteristics (BUFIO)
Symbol
Description
Speed Grade
Units
-2
-1
TBIOCKO_O
Clock to out delay from I to O
0.18
ns
Maximum Frequency
FMAX
I/O clock tree (BUFIO)
710
MHz
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