參數(shù)資料
型號(hào): XC6VCX130T-1FFG1156I
廠商: Xilinx Inc
文件頁數(shù): 25/52頁
文件大?。?/td> 0K
描述: IC FPGA VIRTEX 6 128K 1156FFGBGA
產(chǎn)品培訓(xùn)模塊: Virtex-6 FPGA Overview
產(chǎn)品變化通告: Virtex-6 FIFO Input Logic Reset 18/Apr/2011
標(biāo)準(zhǔn)包裝: 1
系列: Virtex® 6 CXT
LAB/CLB數(shù): 10000
邏輯元件/單元數(shù): 128000
RAM 位總計(jì): 9732096
輸入/輸出數(shù): 600
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 1156-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1156-FCBGA(35x35)
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
31
Input/Output Logic Switching Characteristics
HT (HyperTransport), 2.5V
LDT_25
100
0
0.6
LVPECL (Low-Voltage Positive Emitter-Coupled Logic),
2.5V
LVPECL_25
100
0
0
LVDCI/HSLVDCI, 2.5V
LVDCI_25, HSLVDCI_25
1M
0
1.25
0
LVDCI/HSLVDCI, 1.8V
LVDCI_18, HSLVDCI_18
1M
0
0.9
0
LVDCI/HSLVDCI, 1.5V
LVDCI_15, HSLVDCI_15
1M
0
0.75
0
HSTL (High-Speed Transceiver Logic), Class I & II, with DCI HSTL_I_DCI, HSTL_II_DCI
50
0
VREF
0.75
HSTL, Class III, with DCI
HSTL_III_DCI
50
0
0.9
1.5
HSTL, Class I & II, 1.8V, with DCI
HSTL_I_DCI_18, HSTL_II_DCI_18
50
0
VREF
0.9
HSTL, Class III, 1.8V, with DCI
HSTL_III_DCI_18
50
0
1.1
1.8
SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI SSTL18_I_DCI, SSTL18_II_DCI
50
0
VREF
0.9
SSTL, Class I & II, 2.5V, with DCI
SSTL2_I_DCI, SSTL2_II_DCI
50
0
VREF
1.25
Notes:
1.
CREF is the capacitance of the probe, nominally 0 pF.
2.
The value given is the differential output voltage.
Table 42: ILOGIC Switching Characteristics
Symbol
Description
Speed Grade
Units
-2
-1
Setup/Hold
TICE1CK/TICKCE1
CE1 pin Setup/Hold with respect to CLK
0.27/0.04
ns
TISRCK/TICKSR
SR pin Setup/Hold with respect to CLK
0.96/–0.10
ns
TIDOCK/TIOCKD
D pin Setup/Hold with respect to CLK without Delay
0.10/0.54
ns
TIDOCKD/TIOCKDD
DDLY pin Setup/Hold with respect to CLK (using IODELAY)
0.14/0.42
0.14/0.40
ns
Combinatorial
TIDI
D pin to O pin propagation delay, no Delay
0.20
ns
TIDID
DDLY pin to O pin propagation delay (using IODELAY)
0.25
ns
Sequential Delays
TIDLO
D pin to Q1 pin using flip-flop as a latch without Delay
0.64
ns
TIDLOD
DDLY pin to Q1 pin using flip-flop as a latch (using IODELAY)
0.68
ns
TICKQ
CLK to Q outputs
0.71
ns
TRQ_ILOGIC
SR pin to OQ/TQ out
1.15
ns
TGSRQ_ILOGIC
Global Set/Reset to Q outputs
10.51
ns
Set/Reset
TRPW_ILOGIC
Minimum Pulse Width, SR inputs
1.20
ns, Min
Table 41: Output Delay Measurement Methodology (Cont’d)
Description
I/O Standard
Attribute
RREF
(
)
CREF(1)
(pF)
VMEAS
(V)
VREF
(V)
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