參數(shù)資料
型號： XC6VCX130T-1FFG1156I
廠商： Xilinx Inc
文件頁數(shù)： 43/52頁
文件大?。?/td> 0K
描述： IC FPGA VIRTEX 6 128K 1156FFGBGA
產(chǎn)品培訓模塊： Virtex-6 FPGA Overview
產(chǎn)品變化通告： Virtex-6 FIFO Input Logic Reset 18/Apr/2011
標準包裝： 1
系列： Virtex® 6 CXT
LAB/CLB數(shù)： 10000
邏輯元件/單元數(shù)： 128000
RAM 位總計： 9732096
輸入/輸出數(shù)： 600
電源電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 1156-BBGA，F(xiàn)CBGA
供應商設備封裝： 1156-FCBGA（35x35）
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
48
Virtex-6 CXT Device Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 61. Values are expressed in nanoseconds unless otherwise noted.
Table 61: Global Clock Input Setup and Hold Without MMCM
Symbol
Description
Device
Speed Grade
Units
-2
-1
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)
TPSFD/ TPHFD
Full Delay (Legacy Delay or Default Delay)
Global Clock Input and IFF(2) without MMCM
XC6VCX75T
1.75/–0.01
ns
XC6VCX130T
1.88/–0.11
ns
XC6VCX195T
1.97/–0.14
ns
XC6VCX240T
1.97/–0.14
ns
Notes:
1.
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
2.
IFF = Input Flip-Flop or Latch.
3.
A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0"
is listed, there is no positive hold time.
Table 62: Global Clock Input Setup and Hold With MMCM
Symbol
Description
Device
Speed Grade
Units
-2
-1
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)
TPSMMCMGC/
TPHMMCMGC
No Delay Global Clock Input and IFF(2) with MMCM XC6VCX75T
1.72/–0.22
ns
XC6VCX130T
1.81/–0.21
ns
XC6VCX195T
1.82/–0.20
ns
XC6VCX240T
1.82/–0.20
ns
Notes:
1.
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
2.
IFF = Input Flip-Flop or Latch.
3.
Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 63: Clock-Capable Clock Input Setup and Hold With MMCM
Symbol
Description
Device
Speed Grade
Units
-2
-1
Input Setup and Hold Time Relative to Clock-capable Clock Input Signal for LVCMOS25 Standard.(1)
TPSMMCMCC/
TPHMMCMCC
No Delay Clock-capable Clock Input and IFF(2)
with MMCM
XC6VCX75T
1.86/–0.28
ns
XC6VCX130T
1.93/–0.28
ns
XC6VCX195T
1.96/–0.27
ns
XC6VCX240T
1.96/–0.27
ns
Notes:
1.
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
2.
IFF = Input Flip-Flop or Latch.
3.
Use IBIS to determine any duty-cycle distortion incurred using various standards.
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XC6VCX130T-1FFG484I 功能描述:IC FPGA VIRTEX 6 128K 484FFGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex® 6 CXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
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