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| 型號(hào)： | XC6VCX130T-1FFG1156I |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 24/52頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA VIRTEX 6 128K 1156FFGBGA |
| 產(chǎn)品培訓(xùn)模塊： | Virtex-6 FPGA Overview |
| 產(chǎn)品變化通告： | Virtex-6 FIFO Input Logic Reset 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Virtex® 6 CXT |
| LAB/CLB數(shù)： | 10000 |
| 邏輯元件/單元數(shù)： | 128000 |
| RAM 位總計(jì)： | 9732096 |
| 輸入/輸出數(shù)： | 600 |
| 電源電壓： | 0.95 V ~ 1.05 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 1156-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 1156-FCBGA（35x35） |
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Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
30
Output Delay Measurements
Output delays are measured using a Tektronix P6245
TDS500/600 probe (< 1 pF) across approximately 4" of FR4
microstrip trace. Standard termination was used for all
testing. The propagation delay of the 4" trace is
characterized separately and subtracted from the final
measurement, and is therefore not included in the
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it.
Parameters VREF, RREF, CREF, and VMEAS fully describe
the test conditions for each I/O standard. The most accurate
prediction of propagation delay in any given application can
be obtained through IBIS simulation, using the following
method:
1.
Simulate the output driver of choice into the generalized
test setup, using values from Table 41.
2.
Record the time to VMEAS.
3.
Simulate the output driver of choice into the actual PCB
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
4.
Record the time to VMEAS.
5.
decrease in delay yields the actual propagation delay of
the PCB trace.
X-Ref Target - Figure 14
Figure 14: Single Ended Test Setup
VREF
RREF
VMEAS
(voltage level when taking
delay measurement)
CREF
(probe capacitance)
FPGA Output
ds152_06_042109
X-Ref Target - Figure 15
Figure 15: Differential Test Setup
RREF VMEAS
+
–
CREF
FPGA Output
ds152_07_042109
Table 41: Output Delay Measurement Methodology
Description
I/O Standard
Attribute
RREF
(
)
CREF(1)
(pF)
VMEAS
(V)
VREF
(V)
LVCMOS, 2.5V
LVCMOS25
1M
0
1.25
0
LVCMOS, 1.8V
LVCMOS18
1M
0
0.9
0
LVCMOS, 1.5V
LVCMOS15
1M
0
0.75
0
LVCMOS, 1.2V
LVCMOS12
1M
0
0.75
0
HSTL (High-Speed Transceiver Logic), Class I
HSTL_I
50
0
VREF
0.75
HSTL, Class II
HSTL_II
25
0
VREF
0.75
HSTL, Class III
HSTL_III
50
0
0.9
1.5
HSTL, Class I, 1.8V
HSTL_I_18
50
0
VREF
0.9
HSTL, Class II, 1.8V
HSTL_II_18
25
0
VREF
0.9
HSTL, Class III, 1.8V
HSTL_III_18
50
0
1.1
1.8
SSTL (Stub Series Terminated Logic), Class I, 1.8V
SSTL18_I
50
0
VREF
0.9
SSTL, Class II, 1.8V
SSTL18_II
25
0
VREF
0.9
SSTL, Class I, 2.5V
SSTL2_I
50
0
VREF
1.25
SSTL, Class II, 2.5V
SSTL2_II
25
0
VREF
1.25
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDS_25
100
0
0(2)
1.2
LVDSEXT (LVDS Extended Mode), 2.5V
LVDS_25
100
0
1.2
BLVDS (Bus LVDS), 2.5V
BLVDS_25
100
0
0
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