參數(shù)資料
型號: XCF08PVOG48C
廠商: Xilinx Inc
文件頁數(shù): 10/35頁
文件大?。?/td> 0K
描述: IC PROM SRL 1.8V 8M GATE 48TSOP
產(chǎn)品變化通告: VOG48 New Shipping Trays Notification 25/Apr/2011
標(biāo)準(zhǔn)包裝: 96
可編程類型: 系統(tǒng)內(nèi)可編程
存儲容量: 8Mb
電源電壓: 1.65 V ~ 2 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TFSOP(0.724",18.40mm 寬)
供應(yīng)商設(shè)備封裝: 48-TSOP
包裝: 管件
產(chǎn)品目錄頁面: 601 (CN2011-ZH PDF)
其它名稱: 122-1454-5
Platform Flash In-System Programmable Configuration PROMs
DS123 (v2.18) May 19, 2010
Product Specification
18
R
XCFxxP PROM as Configuration Master with CLK Input Pin as Clock Source
X-Ref Target - Figure 8
Symbol
Description
XCF08P, XCF16P,
XCF32P
Units
Min
Max
THCF
CF hold time to guarantee design revision selection is sampled
when VCCO = 3.3V or 2.5V(11)
300
CF hold time to guarantee design revision selection is sampled
when VCCO = 1.8V(11)
300
TCF
CF to data delay when VCCO = 3.3V or 2.5V
ns
CF to data delay when VCCO = 1.8V
ns
TOE
OE/RESET to data delay(6) when VCCO = 3.3V or 2.5V
25
ns
OE/RESET to data delay(6) when VCCO = 1.8V
25
ns
TCE
CE to data delay(5) when VCCO = 3.3V or 2.5V
25
ns
CE to data delay(5) when VCCO = 1.8V
25
ns
TEOH
Data hold from CE, OE/RESET, or CF when VCCO = 3.3V or 2.5V
5
ns
Data hold from CE, OE/RESET, or CF when VCCO = 1.8V
5
ns
TDF
CE or OE/RESET to data float delay(2) when VCCO = 3.3V or 2.5V
45
ns
CE or OE/RESET to data float delay(2) when VCCO = 1.8V
45
ns
TOECF
OE/RESET to CLKOUT float delay(2) when VCCO = 3.3V or 2.5V
ns
OE/RESET to CLKOUT float delay(2) when VCCO = 1.8V
ns
TCECF
CE to CLKOUT float delay(2) when VCCO = 3.3V or 2.5V
ns
CE to CLKOUT float delay(2) when VCCO = 1.8V
ns
CE
OE/RESET
CLK
CLKOUT
BUSY
(optional)
DATA
TCE
TLC
THC
TOE
THCE
THOE
TCYCO
THB
TSB
TOECC
TCECC
TCLKO
TCOH
TCCDD
ds123_25_110707
TEOH
TDF
Note:Typically, 8 CLKOUT cycles are output after CE rising edge, before CLKOUT
tristates, if OE/RESET remains high, and terminal count has not been reached.
CF
EN_EXT_SEL
REV_SEL[1:0]
TSXT
THXT
TSRV
THRV
TSXT
THXT
TSRV
THRV
TCF
TCFCC
TCECF
TOECF
TDDC
THCF
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