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參數(shù)資料
| 型號： | XCF08PVOG48C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 35/35頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROM SRL 1.8V 8M GATE 48TSOP |
| 產(chǎn)品變化通告： | VOG48 New Shipping Trays Notification 25/Apr/2011 |
| 標準包裝： | 96 |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 存儲容量： | 8Mb |
| 電源電壓： | 1.65 V ~ 2 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 48-TFSOP（0.724"，18.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-TSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 601 (CN2011-ZH PDF) |
| 其它名稱： | 122-1454-5 |
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Platform Flash In-System Programmable Configuration PROMs
DS123 (v2.18) May 19, 2010
Product Specification
9
R
Because of the 8 Mb minimum size requirement for
each revision, a single 16 Mb PROM can only store up
to two separate design revisions: one 16 Mb design
revision, one 8 Mb design revision, or two 8 Mb design
revisions.
A single 8 Mb PROM can store only one 8 Mb design
revision.
Larger design revisions can be split over several cascaded
PROMs. For example, two 32 Mb PROMs can store up to four
separate design revisions: one 64 Mb design revision, two
32 Mb design revisions, three 16 Mb design revisions, four
16 Mb design revisions, and so on. When cascading one
16 Mb PROM and one 8 Mb PROM, there are 24 Mb of
available space, and therefore up to three separate design
revisions can be stored: one 24 Mb design revision, two 8 Mb
design revisions, or three 8 Mb design revisions.
See Figure 5 for a few basic examples of how multiple
revisions can be stored. The design revision partitioning is
handled automatically during file generation in iMPACT.
During the PROM file creation, each design revision is
assigned a revision number:
Revision 0 = '00'
Revision 1 = '01'
Revision 2 = '10'
Revision 3 = '11'
After programming the Platform Flash PROM with a set of
design revisions, a particular design revision can be
selected using the external REV_SEL[1:0] pins or using the
internal programmable design revision control bits. The
EN_EXT_SEL pin determines if the external pins or internal
bits are used to select the design revision. When
EN_EXT_SEL is Low, design revision selection is controlled
by the external Revision Select pins, REV_SEL[1:0]. When
EN_EXT_SEL is High, design revision selection is
controlled by the internal programmable Revision Select
control bits. During power up, the design revision selection
inputs (pins or control bits) are sampled internally. After
power up, the design revision selection inputs are sampled
again when any of the following events occur:
On the rising edge of CE.
On the falling edge of OE/RESET (when CE is Low).
On the rising edge of CF (when CE is Low).
When reconfiguration is initiated by using the JTAG
CONFIG instruction.
The data from the selected design revision is then
presented on the FPGA configuration interface.
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