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參數(shù)資料
| 型號： | XCF08PVOG48C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 3/35頁 |
| 文件大小： | 0K |
| 描述： | IC PROM SRL 1.8V 8M GATE 48TSOP |
| 產(chǎn)品變化通告： | VOG48 New Shipping Trays Notification 25/Apr/2011 |
| 標準包裝： | 96 |
| 可編程類型： | 系統(tǒng)內可編程 |
| 存儲容量： | 8Mb |
| 電源電壓： | 1.65 V ~ 2 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 48-TFSOP（0.724"，18.40mm 寬） |
| 供應商設備封裝： | 48-TSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 601 (CN2011-ZH PDF) |
| 其它名稱： | 122-1454-5 |
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Platform Flash In-System Programmable Configuration PROMs
DS123 (v2.18) May 19, 2010
Product Specification
11
R
Reset and Power-On Reset Activation
At power up, the device requires the VCCINT power supply to
monotonically rise to the nominal operating voltage within
the specified VCCINT rise time. If the power supply cannot
meet this requirement, then the device might not perform
power-on reset properly. During the power-up sequence,
OE/RESET is held Low by the PROM. Once the required
supplies have reached their respective POR (Power On
Reset) thresholds, the OE/RESET release is delayed (TOER
minimum) to allow more margin for the power supplies to
stabilize before initiating configuration. The OE/RESET pin
is connected to an external 4.7 k
Ω pull-up resistor and also
to the target FPGA's INIT pin. For systems utilizing slow-
rising power supplies, an additional power monitoring circuit
can be used to delay the target configuration until the
system power reaches minimum operating voltages by
holding the OE/RESET pin Low. When OE/RESET is
released, the FPGA’s INIT pin is pulled High allowing the
FPGA's configuration sequence to begin. If the power drops
below the power-down threshold (VCCPD), the PROM resets
and OE/RESET is again held Low until the after the POR
threshold is reached. OE/RESET polarity is not
programmable. These power-up requirements are shown
graphically in Figure 6.
For a fully powered Platform Flash PROM, a reset occurs
whenever OE/RESET is asserted (Low) or CE is deasserted
(High). The address counter is reset, CEO is driven High, and
the remaining outputs are placed in a high-impedance state.
Note:
1.
The XCFxxS PROM only requires VCCINT to rise above
its POR threshold before releasing OE/RESET.
2.
The XCFxxP PROM requires both VCCINT to rise above its
POR threshold and for VCCO to reach the recommended
operating voltage level before releasing OE/RESET.
I/O Input Voltage Tolerance and Power Sequencing
The I/Os on each re-programmable Platform Flash PROM
are fully 3.3V-tolerant. This allows 3V CMOS signals to
connect directly to the inputs without damage. The core
power supply (VCCINT), JTAG pin power supply (VCCJ),
output power supply (VCCO), and external 3V CMOS I/O
signals can be applied in any order.
Additionally, for the XCFxxS PROM only, when VCCO is
supplied at 2.5V or 3.3V and VCCINT is supplied at 3.3V, the
I/Os are 5V-tolerant. This allows 5V CMOS signals to
connect directly to the inputs on a powered XCFxxS PROM
without damage. Failure to power the PROM correctly while
supplying a 5V input signal can result in damage to the
XCFxxS device.
X-Ref Target - Figure 6
Figure 6: Platform Flash PROM Power-Up Requirements
TOER
VCCINT
VCCPOR
VCCPD
200 s ramp
50 ms ramp
TOER
TRST
TIME (ms)
A slow-ramping VCCINT supply may still
be below the minimum operating
voltage when OE/RESET is released.
In this case, the configuration
sequence must be delayed until both
VCCINT and VCCO have reached their
recommended operating conditions.
Recommended Operating Range
Delay or Restart
Configuration
ds123_21_103103
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