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| 型號： | XCF08PVOG48C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 17/35頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROM SRL 1.8V 8M GATE 48TSOP |
| 產(chǎn)品變化通告： | VOG48 New Shipping Trays Notification 25/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 存儲容量： | 8Mb |
| 電源電壓： | 1.65 V ~ 2 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 48-TFSOP（0.724"，18.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-TSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 601 (CN2011-ZH PDF) |
| 其它名稱： | 122-1454-5 |
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Platform Flash In-System Programmable Configuration PROMs
DS123 (v2.18) May 19, 2010
Product Specification
24
R
Pinouts and Pin Descriptions
The XCFxxS Platform Flash PROM is available in the VO20 and VOG20 packages. The XCFxxP Platform Flash PROM is
available in the VO48, VOG48, FS48, and FSG48 packages. For package drawings, specifications, and additional
information, see UG112, Device Package User Guide, or the Xilinx Package Specifications.
Note:
1.
VO20/VOG20 denotes a 20-pin (TSSOP) Plastic Thin Shrink Small Outline Package.
2.
VO48/VOG48 denotes a 48-pin (TSOP) Plastic Thin Small Outline Package.
3.
FS48/FSG48 denotes a 48-pin (TFBGA) Plastic Thin Fine Pitch Ball Grid Array (0.8 mm pitch).
XCFxxS Pinouts and Pin Descriptions
XCFxxS VO20/VOG20 Pin Names and Descriptions
Table 12 provides a list of the pin names and descriptions for the XCFxxS 20-pin VO20/VOG20 package.
Table 12: XCFxxS Pin Names and Descriptions
Pin Name
Boundary
Scan Order
Boundary-Scan
Function
Pin Description
20-pin TSSOP
(VO20/VOG20)
D0
4
Data Out
D0 is the DATA output pin to provide data for configuring an
FPGA in serial mode. The D0 output is set to a high-
impedance state during ISPEN (when not clamped).
1
3
Output Enable
CLK
0
Data In
Configuration Clock Input. Each rising edge on the CLK input
increments the internal address counter if the CLK input is
selected, CE is Low, and OE/RESET is High.
3
OE/RESET
20
Data In
Output Enable/Reset (Open-Drain I/O). When Low, this input
holds the address counter reset and the DATA output is in a
high-impedance state. This is a bidirectional open-drain pin
that is held Low while the PROM completes the internal
power-on reset sequence. Polarity is not programmable.
8
19
Data Out
18
Output Enable
CE
15
Data In
Chip Enable Input. When CE is High, the device is put into
low-power standby mode, the address counter is reset, and
the DATA pins are put in a high-impedance state.
10
CF
22
Data Out
Configuration Pulse (Open-Drain Output). Allows JTAG
CONFIG instruction to initiate FPGA configuration without
powering down FPGA. This is an open-drain output that is
pulsed Low by the JTAG CONFIG command.
7
21
Output Enable
CEO
12
Data Out
Chip Enable Output. Chip Enable Output (CEO) is connected
to the CE input of the next PROM in the chain. This output is
Low when CE is Low and OE/RESET input is High, AND the
internal address counter has been incremented beyond its
Terminal Count (TC) value. CEO returns to High when
OE/RESET goes Low or CE goes High.
13
11
Output Enable
TMS
–
Mode Select
JTAG Mode Select Input. The state of TMS on the rising edge
of TCK determines the state transitions at the Test Access
Port (TAP) controller. TMS has an internal 50 k
Ω resistive pull-
up to VCCJ to provide a logic 1 to the device if the pin is not
driven.
5
TCK
–
Clock
JTAG Clock Input. This pin is the JTAG test clock. It
sequences the TAP controller and all the JTAG test and
programming electronics.
6
TDI
–
Data In
JTAG Serial Data Input. This pin is the serial input to all JTAG
instruction and data registers. TDI has an internal 50 k
Ω
resistive pull-up to VCCJ to provide a logic 1 to the device if the
pin is not driven.
4
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