參數(shù)資料
型號(hào)： XCF16PFSG48C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 2/35頁(yè)
文件大?。?/td> 0K
描述： IC PROM SRL 1.8V 16M 48CSBGA
產(chǎn)品變化通告： Package Assemble Change 01/Jan/2007
標(biāo)準(zhǔn)包裝： 108
可編程類(lèi)型： 系統(tǒng)內(nèi)可編程
存儲(chǔ)容量： 16Mb
電源電壓： 1.65 V ~ 2 V
工作溫度： -40°C ~ 85°C
封裝/外殼： 48-BFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 48-CSP（8x9）
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 601 (CN2011-ZH PDF)
其它名稱： 122-1455
Platform Flash In-System Programmable Configuration PROMs
DS123 (v2.18) May 19, 2010
Product Specification
10
R
Initiating FPGA Configuration
The options for initiating FPGA configuration via the
Platform Flash PROM include:
Automatic configuration on power up
Applying an external pulse to the FPGA PROGRAM_B
pin
Applying the JTAG CONFIG instruction to the PROM
Following the FPGA’s power-on sequence or the assertion
of the PROGRAM_B pin, the FPGA’s configuration memory
is cleared, the configuration mode is selected, and the
FPGA is ready to accept a new configuration bitstream. The
FPGA’s PROGRAM_B pin can be controlled by an external
source, or alternatively, the Platform Flash PROMs
incorporate a CF pin that can be tied to the FPGA’s
PROGRAM_B pin. Executing the CONFIG instruction
through JTAG pulses the CF output Low once for
300-500 ns, resetting the FPGA and initiating configuration.
The iMPACT software can issue the JTAG CONFIG
command to initiate FPGA configuration by setting the
“Load FPGA” option.
When using the XCFxxP Platform Flash PROM with design
revisioning enabled, the CF pin should always be connected
to the PROGRAM_B pin on the FPGA to ensure that the
current design revision selection is sampled when the
FPGA is reset. The XCFxxP PROM samples the current
design revision selection from the external REV_SEL pins
or the internal programmable Revision Select bits on the
rising edge of CF. When the JTAG CONFIG command is
executed, the XCFxxP samples the new design revision
selection before initiating the FPGA configuration
sequence. When using the XCFxxP Platform Flash PROM
without design revisioning, if the CF pin is not connected to
the FPGA PROGRAM_B pin, then the XCFxxP CF pin must
be tied High.
X-Ref Target - Figure 5
Figure 5: Design Revision Storage Examples
REV 0
(8 Mbits)
REV 1
(8 Mbits)
REV 2
(8 Mbits)
REV 3
(8 Mbits)
REV 0
(8 Mbits)
REV 1
(8 Mbits)
REV 2
(16 Mbits)
REV 0
(16 Mbits)
REV 1
(16 Mbits)
REV 0
(8 Mbits)
REV 1
(24 Mbits)
REV 0
(32 Mbits)
4 Design Revisions
3 Design Revisions
2 Design Revisions
1 Design Revision
(a) Design Revision storage examples for a single XCF32P PROM
REV 0
(16 Mbits)
REV 1
(16 Mbits)
REV 2
(16 Mbits)
REV 3
(16 Mbits)
REV 0
(16 Mbits)
REV 1
(16 Mbits)
REV 2
(32 Mbits)
REV 0
(32 Mbits)
REV 1
(32 Mbits)
REV 0
(16 Mbits)
REV 1
(16 Mbits)
REV 0
(32 Mbits)
4 Design Revisions
3 Design Revisions
2 Design Revisions
1 Design Revision
(b) Design Revision storage examples spanning two XCF32P PROMs
PROM 0
REV 0
(32 Mbits)
REV 1
(32 Mbits)
PROM 1
ds123_20_102103
相關(guān)PDF資料
PDF描述
AYM22DTBH CONN EDGECARD 44POS R/A .156 SLD
GRM188R61A225ME34D CAP CER 2.2UF 10V 20% X5R 0603
RBC08DREI-S13 CONN EDGECARD 16POS .100 EXTEND
ASM22DTBH CONN EDGECARD 44POS R/A .156 SLD
XCF01SVOG20C IC PROM SRL FOR 1M GATE 20-TSSOP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XCF16PFSG48C4039 制造商:Xilinx 功能描述:
XCF16PFSG48C4118 制造商:Xilinx 功能描述:
XCF16PV 制造商:XILINX 制造商全稱:XILINX 功能描述:Platform Flash In-System Programmable Configuration PROMS
XCF16PV048C 制造商:Xilinx 功能描述:
XCF16PVG 制造商:XILINX 制造商全稱:XILINX 功能描述:Platform Flash In-System Programmable Configuration PROMS
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*