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參數(shù)資料
| 型號： | XCF16PFSG48C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 4/35頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROM SRL 1.8V 16M 48CSBGA |
| 產(chǎn)品變化通告： | Package Assemble Change 01/Jan/2007 |
| 標(biāo)準(zhǔn)包裝： | 108 |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 存儲容量： | 16Mb |
| 電源電壓： | 1.65 V ~ 2 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 48-BFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 48-CSP（8x9） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 601 (CN2011-ZH PDF) |
| 其它名稱： | 122-1455 |
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Platform Flash In-System Programmable Configuration PROMs
DS123 (v2.18) May 19, 2010
Product Specification
12
R
Standby Mode
The PROM enters a low-power standby mode whenever CE is
deasserted (High). In standby mode, the address counter is
reset, CEO is driven High, and the remaining outputs are
placed in a high-impedance state regardless of the state of the
OE/RESET input. For the device to remain in the low-power
standby mode, the JTAG pins TMS, TDI, and TDO must not be
pulled Low, and TCK must be stopped (High or Low).
When using the FPGA DONE signal to drive the PROM CE
pin High to reduce standby power after configuration, an
external pull-up resistor should be used. Typically a 330
Ω
pull-up resistor is used, but refer to the appropriate FPGA
data sheet for the recommended DONE pin pull-up value. If
the DONE circuit is connected to an LED to indicate FPGA
configuration is complete, and is also connected to the
PROM CE pin to enable low-power standby mode, then an
external buffer should be used to drive the LED circuit to
ensure valid transitions on the PROM’s CE pin. If low-power
standby mode is not required for the PROM, then the CE pin
should be connected to ground.
Table 10: Truth Table for XCFxxS PROM Control Inputs
Control Inputs
Internal Address
Outputs
OE/RESET
CE
DATA
CEO
ICC
High
Low
If address
< TC(2) : increment
Active
High
Active
If address
= TC(2) : don't change
High-Z
Low
Reduced
Low
Held reset
High-Z
High
Active
X(1)
High
Held reset
High-Z
High
Standby
Notes:
1.
X = don’t care.
2.
TC = Terminal Count = highest address value.
Table 11: Truth Table for XCFxxP PROM Control Inputs
Control Inputs
Internal Address
Outputs
OE/RESET
CE
CF
BUSY(5)
DATA
CEO
CLKOUT
ICC
High
Low
High
Low
If address
< TC(2) and
address
< EA(3) : increment
Active
High
Active
If address
< TC(2) and
address
= EA(3) : don't change
High-Z
High
High-Z
Reduced
Else
If address
= TC(2) : don't change
High-Z
Low
High-Z
Reduced
High
Low
High
Unchanged
Active and
Unchanged
High
Active
High
Low
↑
X(1)
Reset(4)
Active
High
Active
Low
X
Held reset(4)
High-Z
High
High-Z
Active
X
High
X
Held reset(4)
High-Z
High
High-Z
Standby
Notes:
1.
X = don’t care.
2.
TC = Terminal Count = highest address value.
3.
For the XCFxxP with Design Revisioning enabled, EA = end address (last address in the selected design revision).
4.
For the XCFxxP with Design Revisioning enabled, Reset = address reset to the beginning address of the selected bank. If Design
Revisioning is not enabled, then Reset = address reset to address 0.
5.
The BUSY input is only enabled when the XCFxxP is programmed for parallel data output and decompression is not enabled.
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