參數(shù)資料
型號(hào): XPC850SRVR66BU
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 42/72頁(yè)
文件大?。?/td> 0K
描述: IC MPU POWERQUICC 66MHZ 256-PBGA
標(biāo)準(zhǔn)包裝: 60
系列: MPC8xx
處理器類型: 32-位 MPC8xx PowerQUICC
速度: 66MHz
電壓: 3.3V
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-PBGA(23x23)
包裝: 托盤(pán)
MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
47
CPM Electrical Characteristics
Figure 45. SI Receive Timing Diagram with Normal Clocking (DSC = 0)
82
L1RCLK, L1TCLK frequency (DSC =1)
16.00 or
SYNCCLK/2
MHz
83
L1RCLK, L1TCLK width low (DSC =1)
P + 10
ns
83A
L1RCLK, L1TCLK width high (DSC = 1)3
P + 10
ns
84
L1CLK edge to L1CLKO valid (DSC = 1)
30.00
ns
85
L1RQ valid before falling edge of L1TSYNC4
1.00
L1TCLK
86
L1GR setup time2
42.00
ns
87
L1GR hold time
42.00
ns
88
L1xCLK edge to L1SYNC valid (FSD = 00) CNT =
0000, BYT = 0, DSC = 0)
—0.00
ns
1
The ratio SyncCLK/L1RCLK must be greater than 2.5/1.
2
These specs are valid for IDL mode only.
3
Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns.
4
These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC,
whichever is later.
Table 17. SI Timing (continued)
Num
Characteristic
All Frequencies
Unit
Min
Max
L1RxD
(Input)
79
76
77
74
L1RCLK
(FE=0, CE=0)
(Input)
L1RCLK
(FE=1, CE=1)
(Input)
L1RSYNC
(Input)
L1ST
n
(Output)
71
70
RFSD=1
75
72
73
78
BIT0
71a
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