TWR1 Delay from AS# to IOW# 10 ns
參數(shù)資料
型號(hào): XR16L651CM-F
廠商: Exar Corporation
文件頁數(shù): 38/56頁
文件大?。?/td> 0K
描述: IC UART FIFO 32B 48TQFP
標(biāo)準(zhǔn)包裝: 250
特點(diǎn): *
通道數(shù): 1,UART
FIFO's: 32 字節(jié)
規(guī)程: 打印機(jī),RS232,RS422,RS485
電源電壓: 2.25 V ~ 5.5 V
帶并行端口:
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤
á
XR16L651
REV. 1.3.0
2.25V TO 5.5V UART WITH 32-BYTE FIFO
43
TWR1
Delay from AS# to IOW#
10
ns
TDS2
Data Setup Time (16 Mode, AS# used)
30
20
10
ns
TDH2
Data Hold Time (16 Mode, AS# used)
5
ns
TADS
Address Setup (68 Mode)
15
10
5
ns
TADH
Address Hold (68 Mode)
(top mark date code of "BC YYWW" and older)
15
10
5
ns
TADH
Address Hold (68 Mode)
(top mark date code of "C2 YYWW" and newer)
000
ns
TRWS
R/W# Setup to CS# (68 Mode)
20
15
10
ns
TRDA
Read Data Access (68 mode)
50
45
35
ns
TRDH
Read Data Hold (68 mode)
35
30
25
ns
TWDS
Write Data Setup (68 mode)
15
10
5
ns
TWDH
Write Data Hold (68 Mode)
15
10
5
ns
TRWH
CS# De-asserted to R/W# De-asserted (68
Mode)
20
15
10
ns
TCSL
CS# Width (68 Mode)
50
40
30
ns
TCSD
CS# Cycle Delay (68 Mode)
50
40
30
ns
TAS3
Address Setup Time (PC Mode)
5
ns
TRD3
Delay from AEN# to IOR#
10
ns
TRD4
Delay from IOR# to AEN#
10
ns
TWR2
Delay from AEN# to IOW#
10
ns
TWR3
Delay from IOW# to AEN#
10
ns
TDS3
Data Setup Time (PC Mode)
30
20
10
ns
TDH3
Data Hold Time (PC Mode)
5
ns
TWDO
Delay From IOW# To Output
50
40
ns
TMOD
Delay To Set Interrupt From MODEM Input
50
40
35
ns
TRSI
Delay To Reset Interrupt From IOR#
50
40
35
ns
TSSI
Delay From Stop To Set Interrupt
1
Bclk
TRRI
Delay From IOR# To Reset Interrupt
50
45
40
ns
AC ELECTRICAL CHARACTERISTICS
TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.90V TO 5.5V, 70 PF LOAD
WHERE APPLICABLE
SYMBOL
PARAMETER
LIMITS
2.5
MIN
MAX
LIMITS
3.3
MIN
MAX
LIMITS
5.0
MIN
MAX
UNIT
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