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參數(shù)資料
| 型號： | XR16L651CM-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 54/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO 32B 48TQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 特點： | * |
| 通道數(shù)： | 1，UART |
| FIFO's： | 32 字節(jié) |
| 規(guī)程： | 打印機，RS232，RS422，RS485 |
| 電源電壓： | 2.25 V ~ 5.5 V |
| 帶并行端口： | 是 |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤 |
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XR16L651
REV. 1.3.0
2.25V TO 5.5V UART WITH 32-BYTE FIFO
7
1.0
PRODUCT DESCRIPTION
The XR16L651 (651) is an industry first multi-voltage UART that can operate from 2.25V to 5.5V power
supplies. Its inputs are 5V tolerant to facilitate interconnection to transceiver devices of RS-232, RS-422 or RS-
485. The 651 is software compatible to the industry standard 16C550 with some additional enhanced features.
The 651 provides serial asynchronous receive data synchronization, parallel-to-serial data conversion for the
transmitter section and serial-to-parallel data conversions for receiver section. These functions are necessary
for converting the serial data stream into parallel data that is required with digital data systems.
Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmitted data
to form a data character (character orientated protocol). Data integrity is ensured by attaching a parity bit to the
data character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry
to provide all these functions is fairly complex especially when manufactured on a single integrated silicon
chip. The XR16L651 represents such an integration with greatly enhanced features. The 651 is fabricated with
an advanced CMOS process.
The 651 supports standard 8-bit Intel, Motorola or PC bus interfaces through 2 input selection pins. The Intel
bus uses separate input/output read and write signals for all bus transactions while the Motorola bus uses a
read/write signal and chip select to conduct the same transactions. The PC bus mode associates with the PC
ISA bus and follow the industry standard PC definitions for COM 1-4 serial port addresses. The 651 includes
on-board chip select decode logic and selection for the proper interrupt request. This eliminates the need for
an external logic array device.
The 651 has 32-bytes each of transmit and receive FIFOs, automatic RTS/CTS hardware flow control with
hysteresis, automatic Xon/Xoff and special character software flow control, selectable transmit and receive
FIFO trigger levels, wireless infrared encoder and decoder (IrDA ver. 1.0), programmable baud rate generator
with a prescaler of divide by 1 or 4, and data rates up to 3.125 Mbps with a 16X sampling clock rate.
The 651 is an upward solution that provides 32 bytes of transmit and receive FIFO memory, instead of 16 bytes
provided in the 16C550, or none in the 16C450. The 651 is designed to work with high speed communication
devices, that require fast data processing time. Increased performance is realized in the 651 by the larger
transmit and receive FIFOs. This allows the external processor to handle more networking tasks within a given
time. For example, the standard ST16C550 with a 16 byte FIFO, unloads 16 bytes of receive data in 1.53 ms
(This example uses a character length of 11 bits, including start/stop bits at 115.2Kbps). This means the
external CPU will have to service the receive FIFO at 1.53 ms intervals. However with the 32 byte FIFO in the
651, the data buffer will not require unloading/loading for 3.05 ms. This increases the service interval giving the
external CPU additional time for other applications and reducing the overall UART interrupt servicing time. In
addition, the 4 selectable levels of FIFO trigger interrupt and automatic hardware/software flow control is
uniquely provided for maximum data throughput performance especially when operating in a multi-channel
environment. The combination of the above greatly reduces the bandwidth requirement of the external
controlling CPU, increases performance, and reduces power consumption.
The rich feature set of the 651 is available through internal registers. Automatic hardware/software flow control,
selectable transmit and receive FIFO trigger levels, selectable TX and RX baud rates, infrared encoder/
decoder interface, modem interface controls, and a sleep mode are all standard features. In the PC mode, two
tri-state interrupt lines (IRQB and IRQC) and one selectable open source interrupt output (IRQA) are available.
The open source interrupt scheme allows multiple interrupts to be combined in a “wire-OR” operation, thus
reducing the number of interrupt lines in larger systems. Following a power on reset or an external reset, the
651 is software compatible with previous generation of UARTs, 16C450, 16C550 and ST16C650A.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16L651CMTR-F | 制造商:Exar Corporation 功能描述:UART 1-CH 32Byte FIFO 2.5V/3.3V/5V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:XR16L651CMTR-F |
| XR16L651IM | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| XR16L651IM-F | 功能描述:UART 接口集成電路 UARTW/32BYTEFIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16L651IMTR-F | 制造商:Exar Corporation 功能描述:UART 1-CH 32Byte FIFO 2.5V/3.3V/5V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:XR16L651IMTR-F |
| XR16L784 | 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART |
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