XR16L651
á
2.25V TO 5.5V UART WITH 32-BYTE FIFO
REV. 1.3.0
38
TABLE 13: UART RESET CONDITIONS
REGISTERS
RESET STATE
DLL
Bits 7-0 = 0xXX
DLM
Bits 7-0 = 0xXX
RHR
Bits 7-0 = 0xXX
THR
Bits 7-0 = 0xXX
IER
Bits 7-0 = 0x00
FCR
Bits 7-0 = 0x00
ISR
Bits 7-0 = 0x01
LCR
Bits 7-0 = 0x00
MCR
Bits 7-0 = 0x00
LSR
Bits 7-0 = 0x60
XFR
Bits 7-0 = 0x00
MSR
Bits 3-0 = logic 0
Bits 7-4 = logic levels of the inputs
IRPW
Bits 7-0 = 0x00
SPR
Bits 7-0 = 0xFF
EFR
Bits 7-0 = 0x00
XON1
Bits 7-0 = 0x00
XON2
Bits 7-0 = 0x00
XOFF1
Bits 7-0 = 0x00
XOFF2
Bits 7-0 = 0x00
I/O SIGNALS
RESET STATE
TX
Normal = logic 1
Infrared = logic 0
RTS#
Logic 1
DTR#
Logic 1
OP1#
Logic 1
OP2#
Logic 1
TXRDY#
Logic 0
RXRDY#
Logic 1
INT (16 Mode)
INT# (68 Mode)
IRQA, IRQB, IRQC (PC Mode)
Logic 0
Logic 1
Three-State Condition