FIGURE 31. T
參數(shù)資料
型號: XR16L651IM-F
廠商: Exar Corporation
文件頁數(shù): 48/56頁
文件大?。?/td> 0K
描述: IC UART FIFO 32B 48TQFP
標(biāo)準(zhǔn)包裝: 250
特點: *
通道數(shù): 1,UART
FIFO's: 32 字節(jié)
規(guī)程: 打印機,RS232,RS422,RS485
電源電壓: 2.25 V ~ 5.5 V
帶并行端口:
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤
XR16L651
á
2.25V TO 5.5V UART WITH 32-BYTE FIFO
REV. 1.3.0
52
FIGURE 31. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED]
TX
TXRDY#
IOW#
INT*
D0:D7
S
TXDMA
D0:D7
S
D0:D7
T
D0:D7
S
D0:D7
S
T
D0:D7
S
T
D0:D7
S
T
Start
Bit
Stop
Bit
T
WRI
T
(Unloading)
(Loading data
into FIFO)
Last Data Byte
Transmitted
TX FIFO fills up
to trigger level
TX FIFO drops
below trigger level
At least 1
empty location
in FIFO
T
SRT
TX FIFO
Full
T
WT
T
SI
ISR Read
*INT cleared when the ISR is read or when TX FIFO fills up to trigger level.
IER[1]
enabled
IOR# is shown here as an example. IOR would have the same timing as IOR#, but active high.
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