參數(shù)資料
型號(hào)： XR16L784
廠商： Exar Corporation
英文描述： HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
中文描述： 高性能2.97V至5.5V UART的四
文件頁(yè)數(shù)： 51/52頁(yè)
文件大小： 625K
代理商： XR16L784
á
XR16L784
HIGH PERFORMANCE 5V AND 3.3V QUAD UART
PRELIMINARY
REV. P1.2.0
II
3.1.1 The Global Interrupt Source Registers .................................................................................. 21
Figure 14. The Global Interrupt Registers, INT0, INT1, INT2 and INT3 ........................................... 21
3.1.2 General Purpose 16-bit Timer/Counter. [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (default
0xXX-XX-00-00) ............................................................................................................................. 22
T
ABLE
9: UART C
HANNEL
[3:0] I
NTERRUPT
S
OURCE
E
NCODING
AND
C
LEARING
.................................... 22
Figure 15. Timer/Counter circuit. ....................................................................................................... 22
T
ABLE
10: TIMER CONTROL R
EGISTER
............................................................................................... 22
3.1.3 8XMODE [7:0] (default 0x00) ............................................................................................... 23
3.1.4 REGA [7:0] reserved (default 0x00) ..................................................................................... 23
3.1.5 RESET [7:0] (default 0x00) .................................................................................................... 23
3.1.6 SLEEP [7:0] ....................................................................................................(default 0x00) 24
3.1.7 Device Identification and Revision ......................................................................................... 24
3.1.8 REGB [7:0] .....................................................................................................(default 0x00) 24
3.2 UART CHANNEL CONFIGURATION REGISTERS ................................................................................................. 25
T
ABLE
11: UART CHANNEL CONFIGURATION REGISTERS ........................................................... 25
T
ABLE
12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. S
HADED
BITS
ARE
ENABLED
BY
EFR B
IT
-4. ........................................................................................................................ 26
4.0 Internal Register Descriptions ........................................................................................................... 27
4.1 R
ECEIVE
H
OLDING
R
EGISTER
(RHR) - R
EAD
O
NLY
..................................................................................................... 27
4.2 T
RANSMIT
H
OLDING
R
EGISTER
(THR) - W
RITE
O
NLY
.................................................................................................. 27
4.3 I
NTERRUPT
E
NABLE
R
EGISTER
(IER) - R
EAD
/W
RITE
.................................................................................................... 27
4.3.1 IER versus Receive FIFO Interrupt Mode Operation ............................................................. 27
4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation ................................................. 27
4.4 I
NTERRUPT
S
TATUS
R
EGISTER
(ISR) - R
EAD
O
NLY
..................................................................................................... 28
4.4.1 Interrupt Generation: ............................................................................................................. 29
4.4.2 Interrupt Clearing: .................................................................................................................. 29
T
ABLE
13: I
NTERRUPT
S
OURCE
AND
P
RIORITY
L
EVEL
............................................................................. 29
4.5 FIFO C
ONTROL
R
EGISTER
(FCR) - W
RITE
O
NLY
........................................................................................................ 30
4.6 L
INE
C
ONTROL
R
EGISTER
(LCR) - R
EAD
/W
RITE
.......................................................................................................... 31
T
ABLE
14: T
RANSMIT
AND
R
ECEIVE
FIFO T
RIGGER
T
ABLE
AND
L
EVEL
S
ELECTION
.................................. 31
T
ABLE
15: P
ARITY
SELECTION
................................................................................................................ 32
4.7 M
ODEM
C
ONTROL
R
EGISTER
(MCR) - R
EAD
/W
RITE
.................................................................................................... 33
4.8 L
INE
S
TATUS
R
EGISTER
(LSR) - R
EAD
O
NLY
.............................................................................................................. 34
4.9 M
ODEM
S
TATUS
R
EGISTER
(MSR) - R
EAD
O
NLY
........................................................................................................ 34
4.10 M
ODEM
S
TATUS
R
EGISTER
(MSR) - W
RITE
O
NLY
..................................................................................................... 35
4.11 SCRATCH PAD REGISTER (SPR) - R
EAD
/W
RITE
................................................................................................. 36
4.12 FEATURE CONTROL REGISTER (FCTR) - R
EAD
/W
RITE
..................................................................................... 36
T
ABLE
16: A
UTO
RS485 H
ALF
-
DUPLEX
D
IRECTION
C
ONTROL
D
ELAY
FROM
T
RANSMIT
-
TO
-R
ECEIVE
........ 36
T
ABLE
17: 16 S
ELECTABLE
H
YSTERESIS
L
EVELS
W
HEN
T
RIGGER
T
ABLE
-D
IS
S
ELECTED
....................... 37
4.13 E
NHANCED
F
EATURE
R
EGISTER
(EFR) - R
EAD
/W
RITE
............................................................................................... 38
T
ABLE
18: S
OFTWARE
F
LOW
C
ONTROL
F
UNCTIONS
................................................................................ 38
4.14 TXCNT[7:0]: T
RANSMIT
FIFO L
EVEL
C
OUNTER
- R
EAD
O
NLY
................................................................................... 39
4.15 TXTRG [7:0]: T
RANSMIT
FIFO T
RIGGER
L
EVEL
- W
RITE
O
NLY
.................................................................................. 39
4.16 RXCNT[7:0]: R
ECEIVE
FIFO L
EVEL
C
OUNTER
- R
EAD
O
NLY
..................................................................................... 39
4.17 RXTRG[7:0]: R
ECEIVE
FIFO T
RIGGER
L
EVEL
- W
RITE
O
NLY
.................................................................................... 39
T
ABLE
19: UART RESET CONDITIONS .............................................................................................. 40
ABSOLUTE MAXIMUM RATINGS ................................................................................ 41
ELECTRICAL CHARACTERIISTICS ............................................................................. 41
DC ELECTRICAL CHARACTERISTICS ............................................................................................... 41
Figure 16. XR16L784 VOL Sink Current Chart .................................................................................. 42
Figure 17. XR16L784 VOH Source Current Chart ............................................................................. 42
AC E
LECTRICAL
C
HARACTERISTICS
......................................................................................................... 43
Figure 18. 16 Mode (Intel) Data Bus Read and Write Timing .......................................................... 44
Figure 19. 68 Mode (Motorola) Data Bus Read and Write Timing ................................................... 45
Figure 20. Modem Input/Output Port Delay ...................................................................................... 46
Figure 21. Receive Interrupt Timing [Non-FIFO Mode] .................................................................... 46
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