參數(shù)資料
型號(hào)： XR16L784
廠商： Exar Corporation
英文描述： HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
中文描述： 高性能2.97V至5.5V UART的四
文件頁(yè)數(shù)： 9/52頁(yè)
文件大?。?/td> 625K
代理商： XR16L784
á
REV. 1.2.0
XR16L784
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
9
Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the
operating data rate.
Table 4
shows the standard data rates available with a 14.7456 MHz crystal or external
clock at 16X clock rate. At 8X sampling rate, these data rates would double. When using a non-standard data
rate crystal or external clock, the divisor value can be calculated for channel ‘N’ with the following equation(s).
2.7
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods (see EMSR bit-7). The transmitter sends the start-bit followed by the
number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO
and TSR are reported in the Line Status Register (LSR bit-5 and bit-6).
2.7.1
Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.7.2
Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
Transmitter
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16),
WHEN
8XMODE-
BIT
N
IS
0
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 8),
WHEN
8XMODE-
BIT
N
IS
1
T
ABLE
4: T
YPICAL
DATA
RATES
WITH
A
14.7456 MH
Z
CRYSTAL
OR
EXTERNAL
CLOCK
AT
16X S
AMPLING
O
UTPUT
Data Rate
MCR Bit-7=1
O
UTPUT
Data Rate
MCR Bit-7=0
D
IVISOR
FOR
16x
Clock (Decimal)
D
IVISOR
FOR
16x
Clock (HEX)
DLM
P
ROGRAM
V
ALUE
(HEX)
DLL
P
ROGRAM
V
ALUE
(HEX)
D
ATA
R
ATE
E
RROR
(%)
100
400
2304
900
09
00
0
600
2400
384
180
01
80
0
1200
4800
192
C0
00
C0
0
2400
9600
96
60
00
60
0
4800
19.2k
48
30
00
30
0
9600
38.4k
24
18
00
18
0
19.2k
76.8k
12
0C
00
0C
0
38.4k
153.6k
6
06
00
06
0
57.6k
230.4k
4
04
00
04
0
115.2k
460.8k
2
02
00
02
0
230.4k
921.6k
1
01
00
01
0
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