
XR16L788 OCTAL UART
á
REV. 1.1.4
19
T
ABLE
8: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION.
S
HADED
BITS
ARE
ENABLED
BY
EFR B
IT
-4.
A
DDRESS
A3-A0
R
EG
N
AME
R
EAD
/
W
RITE
B
IT
-7
B
IT
-6
B
IT
-5
B
IT
-4
B
IT
-3
B
IT
-2
B
IT
-1
B
IT
-0
C
OMMENT
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 1
RHR
THR
DLL
DLM
IER
R
W
Bit-7
Bit-7
Bit-7
Bit-7
Bit-6
Bit-6
Bit-6
Bit-6
Bit-5
Bit-5
Bit-5
Bit-5
Bit-4
Bit-4
Bit-4
Bit-4
0
Bit-3
Bit-3
Bit-3
Bit-3
Modem
Status Int.
Enable
Bit-2
Bit-2
Bit-2
Bit-2
RX Line
Status Int.
Enable
Bit-1
Bit-1
Bit-1
Bit-1
Bit-0
Bit-0
Bit-0
Bit-0
RX Data
Int.
Enable
LCR[7]=0
LCR[7]=0
LCR[7]=1
LCR[7]=1
R/W
R/W
R/W
0/
CTS/DSR#
Int. Enable
0/
RTS/DTR#
Int. Enable
0/
Xon/Xoff/
Sp. Char.
Int. Enable
0/
Delta-
Flow Cntl
0/
TX FIFO
Trigger
Set Parity
TX Empty
Int.
Enable
0 0 1 0
ISR
R
0/
FIFOs
Enable
0/
RX FIFO
Trigger
Divisor
Enable
0/
FIFOs
Enable
0/
RX FIFO
Trigger
Set TX
Break
0/
Xoff/spe-
cial char
0/
TX FIFO
Trigger
Even
Parity
INT
Source
Bit-3
DMA
Mode
INT
Source
Bit-2
TX FIFO
Reset
INT
Source
Bit-1
RX FIFO
Reset
INT
Source
Bit-0
FIFOs
Enable
0 0 1 0
FCR
W
0 0 1 1
LCR
R/W
Parity
Enable
Stop Bits
Word
Length
Bit-1
RTS# Pin
Control
Word
Length
Bit-0
DTR# Pin
Control
0 1 0 0
MCR
R/W
0/
BRG
Prescaler
0/
IR
Enable
0/
XonAny
Internal
Lopback
Enable
OP2
2
OP1
2
/
RTS/DTR
Flow Sel
RX Parity
Error
Delta
RI#
0 1 0 1
LSR
R/W
RX FIFO
E
RROR
CD
TSR
Empty
RI
THR
Empty
DSR
RX Break RX Fram-
ing Error
Delta
CD#
Reserved Reserved Reserved Reserved
RX Over-
run
Delta
DSR#
RX Data
Ready
Delta
CTS#
0 1 1 0
MSR
R
CTS
MSR
W
0/
RS485
DLY-3
Bit-7
TRG
Table
Bit-1
Auto
CTS/DSR
Enable
0/
RS485
DLY-2
Bit-6
TRG
Table
Bit-0
Auto
RTS/DTR
Enable
0/
RS485
DLY-1
Bit-5
Auto
RS485
Enable
Special
Char
Select
0/
RS485
DLY-0
Bit-4
Invert IR
RX Input
0 1 1 1
1 0 0 0
SPR
FCTR
R/W
R/W
Bit-3
Bit-2
Bit-1
Bit-0
User Data
RTS/DTR
Hyst Bit-3
RTS/DTR
Hyst Bit-2
RTS/DTR
Hyst Bit-1
RTS/DTR
Hyst Bit-0
1 0 0 1
EFR
R/W
Enable
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[7:5]
MSR[7:4]
Bit-4
Bit-4
Bit-4
Bit-4
Software
Flow Cntl
Bit-3
Software
Flow Cntl
Bit-2
Software
Flow Cntl
Bit-1
Software
Flow Cntl
Bit-0
1 0 1 0
1 0 1 0
1 0 1 1
1 0 1 1
1 1 0 0
TFCNT
TFTRG
RFCNT
RFTRG
XCHAR
R
W
R
W
R
Bit-7
Bit-7
Bit-7
Bit-7
Bit-6
Bit-6
Bit-6
Bit-6
Bit-5
Bit-5
Bit-5
Bit-5
Bit-3
Bit-3
Bit-3
Bit-3
Bit-2
Bit-2
Bit-2
Bit-2
Bit-1
Bit-1
Bit-1
Bit-1
Xon Det.
Indicator
Bit-1
Bit-1
Bit-1
Bit-1
Bit-0
Bit-0
Bit-0
Bit-0
Xoff Det.
Indicator
Bit-0
Bit-0
Bit-0
Bit-0
Self-clear
after read
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
XOFF1
XOFF2
XON1
XON2
W
W
W
W
Bit-7
Bit-7
Bit-7
Bit-7
Bit-6
Bit-6
Bit-6
Bit-6
Bit-5
Bit-5
Bit-5
Bit-5
Bit-4
Bit-4
Bit-4
Bit-4
Bit-3
Bit-3
Bit-3
Bit-3
Bit-2
Bit-2
Bit-2
Bit-2