參數(shù)資料
型號： XR16L788
廠商： Exar Corporation
英文描述： HIGH PERFORMANCE OCTAL UART
中文描述： 高性能八進(jìn)制的UART
文件頁數(shù)： 41/42頁
文件大?。?/td> 557K
代理商： XR16L788
XR17C158
PCI BUS OCTAL UART
REV. 1.1.4
á
I
TABLE OF CONTENTS
GENERAL DESCRIPTION ............................................................................................... 1
A
PPLICATIONS
........................................................................................................................................... 1
NEW F
EATURES
: ...................................................................................................................................... 1
Figure 1. Block Diagram ......................................................................................................................... 1
Figure 2. Pin Out of the Device .............................................................................................................. 2
ORDERING
INFORMATION
............................................................................................................................ 2
PIN DESCRIPTIONS ....................................................................................................... 3
DESCRIPTION .................................................................................................................. 7
1.0 XR16L788 REGISTERS ......................................................................................................................... 7
Figure 3. The XR16L788 Registers ........................................................................................................ 7
1.1
DEVICE CONFIGURATION REGISTER SET ................................................................................... 7
T
ABLE
1: XR16L788 R
EGISTER
S
ETS
....................................................................................................... 8
T
ABLE
2: D
EVICE
C
ONFIGURATION
R
EGISTERS
.......................................................................................... 8
INT0 Channel Interrupt Indicator: ....................................................................................... 9
INT1, INT2 and INT3 Interrupt Source Locator ................................................................. 9
Figure 4. The Global Interrupt Registers, INT0, INT1, INT2 and INT3 ................................................... 9
T
ABLE
3: UART C
HANNEL
[7:0] I
NTERRUPT
S
OURCE
E
NCODING
AND
C
LEARING
...................................... 10
Figure 5. Timer/Counter circuit. ............................................................................................................ 10
T
ABLE
4: TIMER CONTROL R
EGISTER
................................................................................................. 10
2.0 CRYSTAL OSCILLATOR / BUFFER .................................................................................................... 12
3.0 TRANSMIT AND RECEIVE DATA ........................................................................................................ 12
3.1 FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR AND RHR. 12
Figure 6. Typical oscillator connections ................................................................................................ 12
T
ABLE
5: T
RANSMIT
AND
R
ECEIVE
D
ATA
R
EGISTER
, 16C550
COMPATIBLE
............................................... 13
4.0 UART ..................................................................................................................................................... 13
4.1 P
ROGRAMMABLE
B
AUD
R
ATE
G
ENERATOR
........................................................................................................... 13
Figure 7. Baud Rate Generator ............................................................................................................ 14
T
ABLE
6: T
YPICAL
DATA
RATES
WITH
A
14.7456 MH
Z
CRYSTAL
OR
EXTERNAL
CLOCK
AT
16X S
AMPLING
... 14
4.2 A
UTOMATIC
RTS/DTR H
ARDWARE
F
LOW
C
ONTROL
O
PERATION
........................................................................... 14
Figure 8. Auto RTS/DTR and CTS/DSR Flow Control Operation ......................................................... 15
4.3 I
NFRARED
M
ODE
.................................................................................................................................................. 16
Figure 9. Infrared Transmit Data Encoding and Receive Data Decoding ............................................. 16
4.4 I
NTERNAL
L
OOPBACK
........................................................................................................................................... 16
Figure 10. Internal Loop Back .............................................................................................................. 17
4.5 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING. ......................................... 17
T
ABLE
7: UART CHANNEL CONFIGURATION REGISTERS. ............................................................. 18
T
ABLE
8: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. S
HADED
BITS
ARE
ENABLED
BY
EFR B
IT
-4. ............................................................................................................................................. 19
4.6 T
RANSMITTER
...................................................................................................................................................... 20
Figure 11. Transmitter Operation in non-FIFO Mode ........................................................................... 20
Figure 12. Transmitter Operation in FIFO and Flow Control Mode ...................................................... 21
4.7 R
ECEIVER
........................................................................................................................................................... 21
4.8 R
EGISTERS
.......................................................................................................................................................... 21
Figure 13. Receiver Operation in non-FIFO Mode ............................................................................... 22
Figure 14. Receiver Operation in FIFO and Flow Control Mode .......................................................... 22
4.9 IER
VERSUS
R
ECEIVE
FIFO I
NTERRUPT
M
ODE
O
PERATION
.................................................................................. 22
4.10 IER
VERSUS
R
ECEIVE
/T
RANSMIT
FIFO P
OLLED
M
ODE
O
PERATION
..................................................................... 23
4.11 I
NTERRUPT
S
TATUS
R
EGISTER
(ISR) .................................................................................................................. 23
T
ABLE
9: I
NTERRUPT
S
OURCE
AND
P
RIORITY
L
EVEL
................................................................................ 24
T
ABLE
10: T
RANSMIT
AND
R
ECEIVE
FIFO T
RIGGER
L
EVEL
S
ELECTION
..................................................... 25
T
ABLE
11: P
ARITY
SELECTION
................................................................................................................. 26
T
ABLE
12: A
UTO
RS485 H
ALF
-
DUPLEX
D
IRECTION
C
ONTROL
D
ELAY
FROM
T
RANSMIT
-
TO
-R
ECEIVE
.......... 29
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