REV. 1.0.2 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 32-BYTE FIFO LCR[6]: Transmit Break Enable When enabled, the Break control bit " />
參數(shù)資料
型號(hào)： XR16M2650IL32-F
廠(chǎng)商： Exar Corporation
文件頁(yè)數(shù)： 22/47頁(yè)
文件大?。?/td> 0K
描述： IC UART FIFO 32B DUAL 32QFN
標(biāo)準(zhǔn)包裝： 490
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 32 字節(jié)
規(guī)程： RS232，RS422
電源電壓： 1.62 V ~ 3.63 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤(pán)（5x5）
包裝： 托盤(pán)
XR16M2650
29
REV. 1.0.2
HIGH PERFORMANCE LOW VOLTAGE DUART WITH 32-BYTE FIFO
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space", LOW state). This condition remains, until disabled by setting LCR bit-6 to LOW.
Logic 0 = No TX break condition (default).
Logic 1 = Forces the transmitter output (TX) to a “space”, LOW, for alerting the remote receiver of a line
break condition.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL, DLM and DLD) enable.
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers are selected.
4.7
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
Logic 0 = Force DTR# output HIGH (default).
Logic 1 = Force DTR# output LOW.
MCR[1]: RTS# Output
The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by
EFR bit-6. If the modem interface is not used, this output may be used as a general purpose output.
Logic 0 = Force RTS# HIGH (default).
Logic 1 = Force RTS# LOW.
MCR[2]: IrDA RX Inversion or OP1# (legacy term)
When Infrared mode is enabled (MCR[6]=1 and EFR[4]=1), this bit selects the idle state of the encoded IrDA
data. In internal loopback mode, this bit functions like the OP1# in the 16C550.
Logic 0 = Select RX input as active-low encoded IrDA data (Idle state will be low) (default).
Logic 1 = Select RX input as active-high encoded IrDA data (Idle state will be high).
In the Internal Loopback Mode, this bit controls the state of the modem input RI# bit in the MSR register as
shown in Figure 12.
MCR[3]: OP2# Output / INT Output Enable
This bit enables or disables the operation of INT, interrupt output. If INT output is not used, OP2# can be used
as a general purpose output.
Logic 0 = INT (A-B) outputs disabled (three state mode) and OP2# output set HIGH(default).
Logic 1 = INT (A-B) outputs enabled (active mode) and OP2# output set LOW.
MCR[4]: Internal Loopback Enable
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and Figure 12.
相關(guān)PDF資料
PDF描述
1-1776244-9 TERM BLOCK RCPT 19POS VERT 5MM
1-1776244-8 TERM BLOCK RCPT 18POS VERT 5MM
1-1776244-7 TERM BLOCK RCPT 17POS VERT 5MM
1-1776244-6 TERM BLOCK RCPT 16POS VERT 5MM
1-1776244-5 TERM BLOCK RCPT 15POS VERT 5MM
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