REV. 1.0.2 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 32-BYTE FIFO LSR[5]: Transmit Holding Register Empty Flag This bit is the Trans" />
參數(shù)資料
型號: XR16M2650IL32-F
廠商: Exar Corporation
文件頁數(shù): 25/47頁
文件大?。?/td> 0K
描述: IC UART FIFO 32B DUAL 32QFN
標準包裝: 490
特點: *
通道數(shù): 2,DUART
FIFO's: 32 字節(jié)
規(guī)程: RS232,RS422
電源電壓: 1.62 V ~ 3.63 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應商設備封裝: 32-QFN 裸露焊盤(5x5)
包裝: 托盤
XR16M2650
31
REV. 1.0.2
HIGH PERFORMANCE LOW VOLTAGE DUART WITH 32-BYTE FIFO
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. The THR bit is set to HIGH when the last data byte is
transferred from the transmit holding register to the transmit shift register. The bit is reset to LOW concurrently
with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set when the
transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte.
LSR[6]: THR and TSR Empty Flag
This bit is set to HIGH whenever the transmitter goes idle. It is set to LOW whenever either the THR or TSR
contains a data character. In the FIFO mode this bit is set to HIGH whenever the transmit FIFO and transmit
shift register are both empty.
LSR[7]: Receive FIFO Data Error Flag
Logic 0 = No FIFO error (default).
Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error
or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the
RX FIFO.
4.9
Modem Status Register (MSR) - Read Only
This register provides the current state of the modem interface input signals. Lower four bits of this register are
used to indicate the changed information. These bits are set to HIGH whenever a signal from the modem
changes state. These bits may be used for general purpose inputs when they are not used with modem
signals.
MSR[0]: Delta CTS# Input Flag
Logic 0 = No change on CTS# input (default).
Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[1]: Delta DSR# Input Flag
Logic 0 = No change on DSR# input (default).
Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[2]: Delta RI# Input Flag
Logic 0 = No change on RI# input (default).
Logic 1 = The RI# input has changed from a LOW to HIGH, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[3]: Delta CD# Input Flag
Logic 0 = No change on CD# input (default).
Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[4]: CTS Input Status
CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto
CTS (EFR bit-7). Auto CTS flow control allows starting and stopping of local data transmissions based on the
modem CTS# signal. A HIGH on the CTS# pin will stop UART transmitter as soon as the current character has
finished transmission, and a LOW will resume data transmission. Normally MSR bit-4 bit is the complement of
the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The
CTS# input may be used as a general purpose input when the modem interface is not used.
相關(guān)PDF資料
PDF描述
1-1776244-9 TERM BLOCK RCPT 19POS VERT 5MM
1-1776244-8 TERM BLOCK RCPT 18POS VERT 5MM
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