REV. 1.0.2 FIGURE
參數(shù)資料
型號(hào): XR16M2650IL32-F
廠商: Exar Corporation
文件頁(yè)數(shù): 37/47頁(yè)
文件大?。?/td> 0K
描述: IC UART FIFO 32B DUAL 32QFN
標(biāo)準(zhǔn)包裝: 490
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 32 字節(jié)
規(guī)程: RS232,RS422
電源電壓: 1.62 V ~ 3.63 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-QFN 裸露焊盤(5x5)
包裝: 托盤
XR16M2650
42
HIGH PERFORMANCE LOW VOLTAGE DUART WITH 32-BYTE FIFO
REV. 1.0.2
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B
FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B
TX
TXRDY#
IOW#
INT*
TXDMA#
D0:D7
S
D0:D7
T
D0:D7
S
D0:D7
S
T
D0:D7
S
T
D0:D7
S
T
Start
Bit
Stop
Bit
T
WRI
(Unloading)
(Loading data
into FIFO)
Last Data Byte
Transmitted
TX FIFO fills up
to trigger level
TX FIFO drops
below trigger level
Data in
TX FIFO
Empty
T
WT
T
SRT
TX FIFO
Empty
T
S
T
SI
ISR is read
IER[1]
enabled
ISR is read
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
TX
TXRDY#
IOW#
INT*
D0:D7
S
TXDMA
D0:D7
S
D0:D7
T
D0:D7
S
D0:D7
S
T
D0:D7
S
T
D0:D7
S
T
Start
Bit
Stop
Bit
T
WRI
T
(Unloading)
(Loading data
into FIFO)
Last Data Byte
Transmitted
TX FIFO fills up
to trigger level
TX FIFO drops
below trigger level
At least 1
empty location
in FIFO
T
SRT
TX FIFO
Full
T
WT
T
SI
ISR Read
*INT cleared when the ISR is read or when TX FIFO fills up to trigger level.
IER[1]
enabled
相關(guān)PDF資料
PDF描述
1-1776244-9 TERM BLOCK RCPT 19POS VERT 5MM
1-1776244-8 TERM BLOCK RCPT 18POS VERT 5MM
1-1776244-7 TERM BLOCK RCPT 17POS VERT 5MM
1-1776244-6 TERM BLOCK RCPT 16POS VERT 5MM
1-1776244-5 TERM BLOCK RCPT 15POS VERT 5MM
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