參數(shù)資料
型號(hào): XR17C158
廠商: Exar Corporation
英文描述: PCI Bus Octal UART(八通用異步接收器/發(fā)送器(滿足通訊系統(tǒng)中PCI總線和高帶寬要求))
中文描述: PCI總線八路的UART(八通用異步接收器/發(fā)送器(滿足通訊系統(tǒng)中的PCI總線和高帶寬要求))
文件頁數(shù): 16/51頁
文件大?。?/td> 685K
代理商: XR17C158
PCI BUS OCTAL UART
XR17C158
PRELIMINARY
REV. 1.0.0
16
TIMER [15:8] (default 0x00)
Reserved.
TIMERMSB [31:24] and TIMERLSB [23:16]
TIMERMSB and TIMERLSB form a 16-bit value. The
least-significant bit of the timer is being bit [0] of the
TIMERLSB with most-significant-bit being bit [7] in
TIMERMSB. Reading the TIMERCNTL register will
clear its interrupt. Default value is zero upon pow-
erup and reset.
1.2.3
Each bit selects 8X or 16X sampling rate for that
UART channel, bit-0 is channel 0. Logic 0 (default)
selects normal 16X sampling with logic one selects
8X sampling rate. Transmit and receive data rates will
double by selecting 8X.
8XMODE [7:0] (default 0x00)
1.2.4
REGA [15:8] is reserved
(default 0x00)
1.2.5
The 8-bit Reset register [RESET] provides the soft-
ware with the ability to reset the UART(s) when there
is a need. Each bit is self-resetting after it is written a
logic 1 to perform a reset to that channel. All registers
in that channel will be reset to the default condition,
see
Table 18
for details. Bit-0 =1 resets UART chan-
nel 0 with bit-7=1 resets channel 7..
RESET [23:16] (default 0x00)
T
ABLE
7: TIMER CONTROL R
EGISTERS
TIMERCNTL [0]
Logic zero (default) disables Timer-Counter interrupt and logic one enables the interrupt, reading the
TIMERCNTL clears the interrupt.
Logic zero (default) stops/pauses the timer and logic one starts/re-starts the timer/counter.
Logic zero (default) selects re-trigger timer function and logic one selects one-shot (timer function.
Logic zero (default) selects internal and logic one selects external clock to the timer/counter.
Routes the Timer-Counter interrupt to MPIO[0] if MPIOSEL[0]=0 for external event control.
Reserved (defaults to zero)
TIMERCNLT [1]
TIMERCNTL [2]
TIMERCNTL [3]
TIMERCNTL [4]
TIMERCNTL [7:5]
TIMERCNTL Register
Rsvd
Rsvd
Rsvd
MPIO[0]
Control
Clock
Select
Single/
Re-trigger
Start/
Stop
INT
Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
TIMERMSB Register
Bit-15 Bit-14 Bit-13 Bit-12 Bit-11 Bit-10 Bit-9 Bit-8
TIMERLSB Register
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
16-Bit Timer/Counter Programmable Registers
REGA [15:8]
IS
RESERVED
(default 0x00)
Ch-6
Ch-7
Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
8XMODE Register
Individual UART Channel 8X Clock Mode Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Ch-6
Ch-7
Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
RESET Register
Individual UART Channel Reset Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
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