參數(shù)資料
型號： XR17C158
廠商： Exar Corporation
英文描述： PCI Bus Octal UART(八通用異步接收器/發(fā)送器（滿足通訊系統(tǒng)中PCI總線和高帶寬要求）)
中文描述： PCI總線八路的UART（八通用異步接收器/發(fā)送器（滿足通訊系統(tǒng)中的PCI總線和高帶寬要求））
文件頁數(shù)： 32/51頁
文件大?。?/td> 685K
代理商： XR17C158
PCI BUS OCTAL UART
XR17C158
PRELIMINARY
REV. 1.0.0
32
4.8.2
DLM)
The Baud Rate Generator (BRG) is a 16-bit counter
that generates the data rate for the transmitter and
receiver. The rate is programmed through registers
DLL and DLM which are only accessible when LCR
bit-7 is set to logic 1. See Programmable Baud Rate
Generator section for more detail.
4.8.3
Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the inter-
rupts from receive data ready, transmit empty, line
status and modem status registers. These interrupts
are reported in the Interrupt Status Register (ISR)
register and also encoded in INT (INT0-INT3) register
in the Device Configuration Registers.
4.9
IER
VERSUS
R
ECEIVE
FIFO I
NTERRUPT
M
ODE
O
PERATION
When the receive FIFO (FCR BIT-0 = a logic 1) and
receive interrupts (IER BIT-0 = logic 1) are enabled,
the RHR interrupts (see ISR bits 3 and 4) status will
reflect the following:
A.
The receive data available interrupts are issued
to the host when the FIFO has reached the pro-
grammed trigger level. It will be cleared when the
FIFO drops below the programmed trigger level.
B.
FIFO level will be reflected in the ISR register
when the FIFO trigger level is reached. Both the
ISR register status bit and the interrupt will be
cleared when the FIFO drops below the trigger
level.
C.
The receive data ready bit (LSR BIT-0) is set as
soon as a character is transferred from the shift
register to the receive FIFO. It is reset when the
FIFO is empty.
4.10 IER
VERSUS
R
ECEIVE
/T
RANSMIT
FIFO P
OLLED
M
ODE
O
PERATION
When FCR BIT-0 equals a logic 1 for FIFO enable;
resetting IER bits 0-3 enables the 158 in the FIFO
polled mode of operation. Since the receiver and
transmitter have separate bits in the LSR either or
both can be used in the polled mode by selecting re-
spective transmit or receive control bit(s).
A.
LSR BIT-0 indicates there is data in RHR
or
RX
FIFO.
B.
LSR BIT 1-4 provides the type of receive data er-
rors encountered for the data byte in RHR, if any.
C.
LSR BIT-5 indicates THR is empty.
D.
LSR BIT-6 indicates when both the transmit FIFO
and TSR are empty.
E.
LSR BIT-7 indicates the Or’ed function of errors
in the RX FIFO.
Baud Rate Generator Divisors (DLL and
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when
RHR has a data character in the non-FIFO mode
or
when the receive FIFO has reached the programmed
trigger level in the FIFO mode.
Logic 0 = Disable the receive data ready interrupt.
(default)
Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This interrupt is associated with bit-5 in the LSR reg-
ister. An interrupt is issued whenever the THR be-
comes empty or when data in the FIFO falls below
the programmed trigger level.
Logic 0 = Disable Transmit Holding Register empty
interrupt. (default)
Logic 1 = Enable Transmit Holding Register empty
interrupt.
IER[2]: Receive Line Status Interrupt Enable
Any of the LSR register bits 1,2,3 or 4 becomes ac-
tive will generate an interrupt to inform the host con-
troller about the error status of the current data byte
in FIFO.
Logic 0 = Disable the receiver line status interrupt.
(default)
Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
Logic 0 = Disable the modem status register interrupt.
(default)
Logic 1 = Enable the modem status register interrupt.
IER[4]: Reserved
.
IER[5]: Xoff Interrupt Enable (requires EFR bit-
4=1)
Logic 0 = Disable the software flow control, receive
Xoff interrupt. (default)
Logic 1 = Enable the software flow control, receive
Xoff interrupt. See Software Flow Control section for
details.
IER[6]: RTS# Output Interrupt Enable (requires
EFR bit-4=1)
Logic 0 = Disable the RTS# interrupt. (default ).
Logic 1 = Enable the RTS# interrupt. The UART is-
sues an interrupt when the RTS# pin makes a transi-
tion.
IER[7]: CTS# Input Interrupt Enable (requires EFR
bit-4=1)
Logic 0 = Disable the CTS# interrupt. (default).
Logic 1 = Enable the CTS# interrupt. The UART is-
sues an interrupt when CTS# pin makes a transition.
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相關代理商/技術參數(shù)
參數(shù)描述
XR17C158CV 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR17C158CV-0A-EVB 功能描述:UART 接口集成電路 Supports C158 144 ld TQFP, PCI Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR17C158CV-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR17C158CVTR-F 制造商:Exar Corporation 功能描述:UART 8-CH 64Byte FIFO 5V 144-Pin LQFP T/R 制造商:Exar Corporation 功能描述:XR17C158CVTR-F
XR17C158IV 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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