參數(shù)資料
型號： XR17C158
廠商： Exar Corporation
英文描述： PCI Bus Octal UART(八通用異步接收器/發(fā)送器（滿足通訊系統(tǒng)中PCI總線和高帶寬要求）)
中文描述： PCI總線八路的UART（八通用異步接收器/發(fā)送器（滿足通訊系統(tǒng)中的PCI總線和高帶寬要求））
文件頁數(shù)： 36/51頁
文件大?。?/td> 685K
代理商： XR17C158
PCI BUS OCTAL UART
XR17C158
PRELIMINARY
REV. 1.0.0
36
2=0. If the modem interface is not used, this output
may be used for general purpose.
Logic 0 = Force RTS# output to a logic 1. (default)
Logic 1 = Force RTS# output to a logic 0.
MCR[2]: DTR# or RTS# for Auto Flow Control
DTR# or RTS# auto hardware flow control select.
This bit is in effect only when auto RTS/DTR is en-
abled by EFR bit-6.
Logic 0 = RTS# pin is used for auto hardware flow
control.
Logic 1 = DTR# pin is used for auto hardware flow
control.
MCR[3]:
Reserved. Logic zero is default.
MCR[4]: Internal Loopback Enable
Logic 0 = Disable loopback mode. (default)
Logic 1 = Enable local loopback mode, see loop-
back section and
Figure 11
.
MCR[5]: Xon-Any Enable
Logic 0 = Disable Xon-Any function (for 16C550
compatibility). (default).
Logic 1 = Enable Xon-Any function. In this mode
any RX character received will enable Xon, resume
data transmission.
MCR[6]: Infrared Encoder/Decoder Enable
Logic 0 = Enable the standard modem receive and
transmit input/output interface. (default)
Logic 1 = Enable infrared IrDA receive and transmit
inputs/outputs. While in this mode, the TX/RX out-
put/input are routed to the infrared encoder/
decoder. The data input and output levels will con-
form to the IrDA infrared interface requirement. As
such, while in this mode the infrared TX output will
be a logic 0 during idle data conditions. FCTR bit-4
may be selected to invert the RX input signal level
going to the decoder for infrared modules that pro-
vide rather an inverted output.
MCR[7]: Clock Prescaler Select
Logic 0 = Divide by one. The input clock from the
crystal or external clock is fed directly to the Pro-
grammable Baud Rate Generator without further
modification, i.e., divide by one. (default).
Logic 1 = Divide by four. The prescaler divides the
input clock from the crystal or external clock by four
and feeds it to the Programmable Baud Rate Gen-
erator, hence, data rates become one forth.
Line Status Register (LSR)
This register provides the status of data transfers be-
tween the UART and the host.
LSR[0]: Receive Data Ready Indicator
Logic 0 = No data in receive holding register or
FIFO. (default).
Logic 1 = Data has been received and is saved in
the receive holding register or FIFO.
LSR[1]: Receiver Overrun Flag
Logic 0 = No overrun error. (default)
Logic 1 = Overrun error. A data overrun error condi-
tion occurred in the receive shift register. This hap-
pens when additional data arrives while the FIFO is
full. In this case the previous data in the receive
shift register is overwritten. Note that under this
condition the data byte in the receive shift register
is not transferred into the FIFO, therefore the data
in the FIFO is not corrupted by the error.
LSR[2]: Receive Data Parity Error Flag
Logic 0 = No parity error. (default)
Logic 1 = Parity error. The receive character in
RHR does not have correct parity information and
is suspect. This error is associated with the char-
acter available for reading in RHR.
LSR[3]: Receive Data Framing Error Flag
Logic 0 = No framing error. (default)
Logic 1 = Framing error. The receive character did
not have a valid stop bit(s). This error is associated
with the character available for reading in RHR.
LSR[4]: Receive Break Flag
Logic 0 = No break condition. (default)
Logic 1 = The receiver received a break signal (RX
was a logic 0 for one character frame time). In the
FIFO mode, only one break character is loaded into
the FIFO. The break indication remains until the RX
input returns to the idle condition, “mark” or logic 1.
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indi-
cator. This bit indicates that the transmitter is ready to
accept a new character for transmission. In addition,
this bit causes the UART to issue an interrupt to the
host when the THR interrupt enable is set. The THR
bit is set to a logic 1 when the last data byte is trans-
ferred from the transmit holding register to the trans-
mit shift register. The bit is reset to logic 0 concurrent-
ly with the data loading to the transmit holding regis-
ter by the host. In the FIFO mode this bit is set when
the transmit FIFO is empty; it is cleared when at least
1 byte is written to the transmit FIFO.
LSR[6]: Transmit Shift Register Empty Flag
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相關代理商/技術參數(shù)
參數(shù)描述
XR17C158CV 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR17C158CV-0A-EVB 功能描述:UART 接口集成電路 Supports C158 144 ld TQFP, PCI Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR17C158CV-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR17C158CVTR-F 制造商:Exar Corporation 功能描述:UART 8-CH 64Byte FIFO 5V 144-Pin LQFP T/R 制造商:Exar Corporation 功能描述:XR17C158CVTR-F
XR17C158IV 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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