參數(shù)資料
型號(hào): XR17V252IM-F
廠商: Exar Corporation
文件頁數(shù): 16/69頁
文件大小: 0K
描述: IC UART PCI BUS DUAL 100TQFP
標(biāo)準(zhǔn)包裝: 90
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS485
電源電壓: 3.3V,5V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 托盤
XR17V252
23
REV. 1.0.2
66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT
MPIOINT [7:0] (default 0x00)
Enable multipurpose input pin interrupt. If the pin is selected by MPIOSEL as input then bit [0] enables input
pin 0 for interrupt, and bit [7] enables input pin 7. No interrupt is enable if the pin is selected to be an output.
The interrupt is edge sensing and determined by MPIOINV and MPIOLVL registers. The MPIO interrupt clears
after a read to register MPIOLVL. The combination of MPIOLVL and MPIOINV determines the interrupt being
active LOW or active high, it’s level trigger. Logic LOW (default) disables the pin’s interrupt and logic HIGH
enables it.
MPIOLVL [7:0] (default 0x00)
Output pin level control and input level status. The status of the input pin(s) is read on this register and output
pins are controlled on this register. A logic 0 (default) sets the output to LOW and a logic 1 sets the output pin
to HIGH. The MPIO interrupt will clear upon reading this register.
MPIO3T [7:0] (default 0x00)
Output pin tri-state control. A logic 0 (default) sets the output to active level per register MPIOBIT settling, a
logic 1 sets the output pin to tri-state.
MPIOINV [7:0] (default 0x00)
Input inversion control. A logic 0 (default) does not invert the input pin logic. A logic 1 inverts the input logic
level.
MPIO6
MPIO7
MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIOINT Register
Multipurpose Input/Output Interrupt Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
MPIO6
MPIO7
MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIOLVL Register
Multipurpose Output Level Control
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
MPIO6
MPIO7
MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIO3T Register
Multipurpose Output 3-state Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
MPIO6
MPIO7
MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIOINV Register
Multipurpose Input Signal Inversion Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
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