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XR17V252
56
66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT
REV. 1.0.2
TABLE 21: UART RESET CONDITIONS
REGISTERS
RESET STATE
I/O SIGNALS
RESET STATE
DLL
Bits [7:0] = 0x01
TX[ch-1:0]
HIGH
DLM
Bits [7:0] = 0x00
IRTX[ch-1:0]
LOW
DLD
Bits [7:0] = 0x00
RTS#[ch-1:0]
HIGH
RHR
Bits [7:0] = 0xXX
DTR#[ch-1:0]
HIGH
THR
Bits [7:0] = 0xXX
EECK
LOW
IER
Bits [7:0] = 0x00
EECS
LOW
FCR
Bits [7:0] = 0x00
EEDI
LOW
ISR
Bits [7:0] = 0x01
LCR
Bits [7:0] = 0x00
MCR
Bits [7:0] = 0x00
LSR
Bits [7:0] = 0x60
MSR
Bits [3:0] = logic 0
Bits [7:4] = logic levels of the inputs
SPR
Bits [7:0] = 0xFF
FCTR
Bits [7:0] = 0x00
EFR
Bits [7:0] = 0x00
TFCNT
Bits [7:0] = 0x00
TFTRG
Bits [7:0] = 0x00
RFCNT
Bits [7:0] = 0x00
RFTRG
Bits [7:0] = 0x00
XCHAR
Bits [7:0] = 0x00
XON1
Bits [7:0] = 0x00
XON2
Bits [7:0] = 0x00
XOFF1
Bits [7:0] = 0x00
XOFF2
Bits [7:0] = 0x00