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參數(shù)資料
| 型號(hào)： | XR20M1280L24-0B-EB |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 28/63頁(yè) |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XR20M128024 |
| 產(chǎn)品培訓(xùn)模塊： | XR21V141x Full-Speed USB UART Family UARTs with Integrated Level Shifters |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，UART |
| 已用 IC / 零件： | XR20M1280L24 |
| 已供物品： | 板 |
| 其它名稱： | 1016-1631 |
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XR20M1280
34
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
3.5
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
enable the wake up interrupt. They are defined as follows:
FCR[0]: TX and RX FIFO Enable
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No receive FIFO reset (default)
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: Enable wake up interrupt (requires EFR bit-4 = 1)
Logic 0 = Disable the wake up interrupt (default).
Logic 1 = Enable the wake up interrupt.
Please refer to “Section 1.20.3, Wake-up Interrupt” on page 25.
FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4 = 1)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load. Table 13 below shows the selections. Note that the
receiver and the transmitter cannot use different trigger tables. Whichever selection is made last applies to
both the RX and TX side.
FCR[7:6]: Receive FIFO Trigger Select
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level. Table 13 shows the complete selections.
Note that the receiver and the transmitter cannot use different trigger tables. Whichever selection is made last
applies to both the RX and TX side.
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| XR20M1280L32-0B-EB | 功能描述:UART 接口集成電路 EVAL F/M1280 QFN32 SPI INTERFACE RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR20M1280L40-0A-EB | 功能描述:UART 接口集成電路 EVAL F/M1280 QFN40 I2C INTERFACE RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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| XR20V2170 | 制造商:EXAR 制造商全稱:EXAR 功能描述:I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER |
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