REV. 1.0.0 EFR[6]: Auto RTS Flow Control Enable RTS# output may be u" />
參數(shù)資料
型號(hào)： XR20M1280L24-0B-EB
廠商： Exar Corporation
文件頁數(shù)： 43/63頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR20M128024
產(chǎn)品培訓(xùn)模塊： XR21V141x Full-Speed USB UART Family
UARTs with Integrated Level Shifters
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，UART
已用 IC / 零件： XR20M1280L24
已供物品： 板
其它名稱： 1016-1631
XR20M1280
48
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and
RTS de-asserts HIGH at the next upper trigger level/hysteresis level. RTS# will return LOW when FIFO data
falls below the next lower trigger level/hysteresis level. The RTS# output must be asserted (LOW) before the
auto RTS can take effect. RTS# pin will function as a general purpose output when hardware flow control is
disabled.
Logic 0 = Automatic RTS flow control is disabled (default).
Logic 1 = Enable Automatic RTS flow control.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
Logic 0 = Automatic CTS flow control is disabled (default).
Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts to logic
1. Data transmission resumes when CTS# returns to a logic 0.
3.20
Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, see Table 8. The xoff2 is also used as auto address detect register when the auto 9-bit mode
3.21
GPIO Interrupt Enable Register (GPIOINT) - Read/Write
If a GPIO has been configured as an input, this register selects which inputs can generate a GPIO interrupt.
This register controls GPIO[7:0] when SFR[1] = 0 and GPIO[15:8] when SFR[1] = 1.
Logic 0 = GPIO interrupt for this input pin is not enabled.
Logic 1 = GPIO interrupt for this input pin is enabled.
3.22
GPIO Three-State Control Register (GPIO3T) - Read/Write
If a GPIO has been configured as an output, this register selects which outputs will be in three-state mode.
This register controls GPIO[7:0] when SFR[1] = 0 and GPIO[15:8] when SFR[1] = 1.
Logic 0 = GPIO output is in active mode and can be controlled via GPIOLVL register.
Logic 1 = GPIO output is in three-state mode.
3.23
GPIO Polarity Control Register (GPIOINV) - Read/Write
If a GPIO has been configured as an interrupt, this register selects the polarity that can generate a GPIO
interrupt. This register controls GPIO[7:0] when SFR[1] = 0 and GPIO[15:8] when SFR[1] = 1.
Logic 0 = GPIO interrupt is generated when this input pin transitions from low to high. RD GPIO LVL returns
GPIO pin state.
Logic 1 = GPIO interrupt is generated when this input pin transitions from high to low. RD GPIO LVL returns
inverted GPIO pin state.
3.24
GPIO Select Register (GPIOSEL) - Read/Write
This register selects where a GPIO is an input or an output.
Logic 0 = GPIO is an output.
Logic 1 = GPIO is an input (default).
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