REV. 1.0.0 1.1.2 I2
參數資料
型號: XR20M1280L24-0B-EB
廠商: Exar Corporation
文件頁數: 62/63頁
文件大小: 0K
描述: EVAL BOARD FOR XR20M128024
產品培訓模塊: XR21V141x Full-Speed USB UART Family
UARTs with Integrated Level Shifters
標準包裝: 1
主要目的: 接口,UART
已用 IC / 零件: XR20M1280L24
已供物品:
其它名稱: 1016-1631
XR20M1280
8
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
1.1.2
I2C-bus Addressing
There could be many devices on the I2C-bus. To distinguish itself from the other devices on the I2C-bus, there
are eight possible slave addresses that can be selected for the XR20M1280 using the A1 and A0 address
lines. Table 1 below shows the different addresses that can be selected. Note that there are two different
ways to select each I2C address.
TABLE 1: XR20M1280 I C ADDRESS MAP
C ADDRESS
VCC
0x60 (0110 000X)
VCC
GND
0x62 (0110 001X)
VCC
SCL
0x64 (0110 010X)
VCC
SDA
0x66 (0110 011X)
GND
VCC
0x68 (0110 100X)
GND
0x6A (0110 101X)
GND
SCL
0x6C (0110 110X)
GND
SDA
0x6E (0110 111X)
SCL
VCC
0x60 (0110 000X)
SCL
GND
0x62 (0110 001X)
SCL
0x64 (0110 010X)
SCL
SDA
0x66 (0110 011X)
SDA
VCC
0x68 (0110 100X)
SDA
GND
0x6A (0110 101X)
SDA
SCL
0x6C (0110 110X)
SDA
0x6E (0110 111X)
An I2C sub-address is sent by the I2C master following the slave address. The sub-address contains the
UART register address being accessed. A read or write transaction is determined by bit-0 of the slave
address. If bit-0 is’0’, then it is a write transaction. If bit-0 is ’1’, then it is a read transaction. If bit-0 is a logic
1, then it is a read transaction. Table 2 below lists the functions of the bits in the I2C sub-address.
TABLE 2: I C SUB-ADDRESS (REGISTER ADDRESS)
BIT
FUNCTION
7:6
Reserved
5:3
UART Internal Register Address A2:A0
2:1
UART Channel Select
’00’ = UART Channel, other values are reserved
0
Reserved
After the last read or write transaction, the I2C-bus master will set the SCL signal back to its idle state (HIGH).
2
A1
A0
I2
2
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