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參數(shù)資料
| 型號(hào)： | XR20M1280L24-0B-EB |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 7/63頁(yè) |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XR20M128024 |
| 產(chǎn)品培訓(xùn)模塊： | XR21V141x Full-Speed USB UART Family UARTs with Integrated Level Shifters |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，UART |
| 已用 IC / 零件： | XR20M1280L24 |
| 已供物品： | 板 |
| 其它名稱： | 1016-1631 |
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XR20M1280
15
REV. 1.0.0
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
1.8
Programmable Baud Rate Generator with Fractional Divisor
The M1280 has independent Baud Rate Generators (BRGs) with prescalers for the transmitter and receiver.
The prescalers are controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescalers
to divide the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG
further divides this clock by a programmable divisor between 1 and (216 - 0.0625) in increments of 0.0625 (1/
16) to obtain a 16X or 8X or 4X sampling clock of the serial data rate. The sampling clock is used by the
transmitter for data bit shifting and receiver for data sampling.
The BRG divisor (DLL, DLM, and DLD registers) defaults to the value of ’1’ (DLL = 0x01, DLM = 0x00 and DLD
= 0x00) during power-on reset. The DLL and DLM registers provide the integer part of the divisor and the DLD
register provides the fractional part of the divisor. The four lower bits of the DLD are used to select a value from
0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). The divisor values can be calculated with the following
equations:
Divisor = (XTAL1 clock frequency / prescaler) / (serial data rate * 16), with 16X mode, DLD[5:4] = ’00’
Divisor = (XTAL1 clock frequency / prescaler / (serial data rate * 8), with 8X mode, DLD[5:4] = ’01’
Divisor = (XTAL1 clock frequency / prescaler / (serial data rate * 4), with 4X mode, DLD[5:4] = ’10’
Integer Divisor = TRUNC (Divisor)
Fractional Divisor = Divisor - Integer Divisor
DLM = Integer Divisor / 256
DLL = Integer Divisor & 256
DLD = TRUNC(Fractional Divisor * 16)
The BRG divisors can be calculated using the following formulas:
In the formulas above, please note that TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.
1.8.1
Fractional BRG Example
For example, if the crystal clock is 24MHz, prescaler is 1, and the sampling mode is 16X, the divisor for a baud
rate of 38400bps would be:
Divisor = (24000000 / 1) / (38400 * 16) = 39.0625
Integer Divisor = TRUNC (39.0625) = 39
Fractional Divisor = 39.0625 - 39 = 0.0625
DLM = 39 / 256 = 0 = 0x00
DLL = 39 & 256 = 39 = 0x27
DLD = 0.0625 * 16 = 1 = 0x1
Table 6 shows the standard data rates available with a 24MHz crystal or external clock at 16X clock rate. If the
pre-scaler is used (MCR bit-7 = 1), the output data rate will be 4 times less than that shown in Table 6. At 8X
sampling rate, these data rates would double. And at 4X sampling rate, they would quadruple. Also, when
using 8X sampling mode, please note that the bit-time will have a jitter (+/- 1/16) whenever the DLD is non-zero
and is an odd number.
1.8.2
Independent TX/RX BRG
The XR20M1280 has two independent sets of TX and RX baud rate generator. See Figure 13. TX and RX can
use different baud rates by setting DLD, DLL and DLM register. For example, TX can transmit data to the
remote UART at 9600 bps while RX receives data from remote UART at 921.6 Kbps. For the baud rate setting,
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