REV. 1.0.0 EMSR[4]: Modem Outputs Three-State Control
參數(shù)資料
型號(hào)： XR20M1280L24-0B-EB
廠商： Exar Corporation
文件頁(yè)數(shù)： 39/63頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR20M128024
產(chǎn)品培訓(xùn)模塊： XR21V141x Full-Speed USB UART Family
UARTs with Integrated Level Shifters
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，UART
已用 IC / 零件： XR20M1280L24
已供物品： 板
其它名稱： 1016-1631
XR20M1280
44
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
EMSR[4]: Modem Outputs Three-State Control
Logic 0 = TX, RTS#, and DTR# outputs are active (default).
Logic 1 = TX, RTS#, and DTR# outputs are in three-state mode.
EMSR[5]: Reserved
This bit is reserved and should be ’0’.
EMSR[6]: LSR Interrupt Mode
Logic 0 = LSR Interrupt Delayed (default). LSR bits 2, 3, and 4 will generate an interrupt when the character
with the error is in the RHR.
Logic 1 = LSR Interrupt Immediate. LSR bits 2, 3, and 4 will generate an interrupt as soon as the character is
received into the FIFO.
EMSR[7]: Xoff/Special character Interrupt Mode Select
This bit selects how the Xoff and Special character interrupt is cleared. The XON interrupt can only be cleared
by reading the ISR register.
Logic 0 = Xoff interrupt is cleared by either reading ISR register or when an XON character is received.
Special character interrupt is cleared by either reading ISR register or when next character is received.
(default).
Logic 1 = Xoff/Special character interrupt can only be cleared by reading the ISR register.
3.15
Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write
These registers make-up the value of the baud rate divisor. The M1280 has different DLL, DLM and DLD for
transmitter and receiver. It provides more convenience for the transmitter and receiver to transmit data with
different rate. The M1280 uses DLD[7:6] to select TX or RX. Then it provides DLD[5:0] to select the sampling
frequency and fractional baud rate divisor. The concatenation of the contents of DLM and DLL gives the 16-bit
divisor value. The value is added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must be
enabled via EFR bit-4 before it can be accessed. See Table 17 below and See ”Section 1.8, Programmable
DLD[5:4]: Sampling Rate Select
These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will
double if the 8X mode is selected and will quadruple if the 4X mode is selected. See Table 17 below.
TABLE 17: SAMPLING RATE SELECT
SAMPLING RATE
0
16X
0
1
8X
1
X
4X
DLD[6]: Independent BRG enable
Logic 0 = The Transmitter and Receiver uses the same Baud Rate Generator. (default).
Logic 1 = The Transmitter and Receiver uses different Baud Rate Generators. Use DLD[7] for selecting
which baud rate generator to configure.
DLD[5]
DLD[4]
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