REV. 1.1.1 3.0 UART INTERNAL REGISTERS Each of the UART channel in the M752 has i" />
參數(shù)資料
型號(hào)： XR68M752IM48-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 17/54頁(yè)
文件大?。?/td> 0K
描述： IC UART FIFO 64B DUAL 48TQFP
標(biāo)準(zhǔn)包裝： 250
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 64 字節(jié)
規(guī)程： RS232，RS422，RS485
電源電壓： 1.62 V ~ 3.63 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤
其它名稱： 1016-1479
1016-1479-ND
1016-1642
XR68M752IM48-F-ND
XR16M752/XR68M752
24
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
REV. 1.1.1
3.0 UART INTERNAL REGISTERS
Each of the UART channel in the M752 has its own set of configuration registers selected by address lines A0,
A1 and A2 with CSA# or CSB# selecting the channel. The complete register set is shown on Table 7 and
TABLE 7: UART CHANNEL A AND B UART INTERNAL REGISTERS
ADDRESSES
REGISTER
READ/WRITE
COMMENTS
16C550 COMPATIBLE REGISTERS
0 0 0
RHR - Receive Holding Register
THR - Transmit Holding Register
Read-only
Write-only
LCR[7] = 0
0 0 0
DLL - Divisor LSB
Read/Write
LCR[7] = 1, LCR
≠ 0xBF
0 0 1
DLM - Divisor MSB
Read/Write
0 1 0
DLD - Divisor Fractional
Read/Write
LCR[7] = 1, LCR
≠ 0xBF,
EFR[4] = 1
0 0 1
IER - Interrupt Enable Register
Read/Write
LCR[7] = 0
0 1 0
ISR - Interrupt Status Register
FCR - FIFO Control Register
Read-only
Write-only
0 1 1
LCR - Line Control Register
Read/Write
1 0 0
MCR - Modem Control Register
Read/Write
LCR
≠ 0xBF
1 0 1
LSR - Line Status Register
Read-only
1 1 0
MSR - Modem Status Register
Read-only
See
1 1 1
SPR - Scratch Pad Register
Read/Write
See
1 1 0
TCR - Transmission Control Register
Read/Write
See
1 1 1
TLR - Trigger Level Register
Read/Write
See
1 1 1
FIFO Rdy - FIFO Ready Register
Read-only
See
ENHANCED REGISTERS
0 1 0
EFR - Enhanced Function Register
Read/Write
LCR = 0xBF
1 0 0
Xon-1 - Xon Character 1
Read/Write
1 0 1
Xon-2 - Xon Character 2
Read/Write
1 1 0
Xoff-1 - Xoff Character 1
Read/Write
1 1 1
Xoff-2 - Xoff Character 2
Read/Write
A2 A1 A0
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