參數(shù)資料
型號: XRT16C854
廠商: Exar Corporation
英文描述: 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
中文描述: 2.97V至5.5V四路UART的128字節(jié)FIFO
文件頁數(shù): 24/54頁
文件大小: 485K
代理商: XRT16C854
XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
xr
REV. 3.0.1
24
.
T
ABLE
9: INTERNAL REGISTERS DESCRIPTION.
S
HADED
BITS
ARE
ENABLED
WHEN
EFR B
IT
-4=1
A
DDRESS
A2-A0
R
EG
N
AME
R
EAD
/
W
RITE
B
IT
-7
B
IT
-6
B
IT
-5
B
IT
-4
B
IT
-3
B
IT
-2
B
IT
-1
B
IT
-0
C
OMMENT
16C550 Compatible Registers
0 0 0
RHR
RD
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7] = 0
0 0 0
THR
WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0 0 1
IER
RD/WR
0/
0/
0/
0/
Modem
Stat. Int.
Enable
RX Line
Stat.
Int.
Enable
TX
Empty
Int
Enable
RX
Data
Int.
Enable
CTS#
Int.
Enable
RTS#
Int.
Enable
Xoff Int.
Enable
Sleep
Mode
Enable
0 1 0
ISR
RD
FIFOs
Enabled
FIFOs
Enabled
0/
0/
INT
Source
Bit-3
INT
Source
Bit-2
INT
Source
Bit-1
INT
Source
Bit-0
INT
Source
Bit-5
INT
Source
Bit-4
0 1 0
FCR
WR
RX FIFO
Trigger
RX FIFO
Trigger
0/
0/
DMA
Mode
Enable
TX
FIFO
Reset
RX
FIFO
Reset
FIFOs
Enable
TX FIFO
Trigger
TX FIFO
Trigger
0 1 1
LCR
RD/WR
Divisor
Enable
Set TX
Break
Set Par-
ity
Even
Parity
Parity
Enable
Stop
Bits
Word
Length
Bit-1
Word
Length
Bit-0
1 0 0
MCR
RD/WR
0/
0/
0/
Internal
Lopback
Enable
INT Out-
put
Enable
(OP2#)
Rsvd
(OP1#)
RTS#
Output
Control
DTR#
Output
Control
LCR[7] = 0
BRG
Pres-
caler
IR Mode
ENable
XonAny
1 0 1
LSR
RD
RX FIFO
Global
Error
THR &
TSR
Empty
THR
Empty
RX
Break
RX Fram-
ing Error
RX
Parity
Error
RX
Over-
run
Error
RX
Data
Ready
1 1 0
MSR
RD
CD#
Input
RI#
Input
DSR#
Input
CTS#
Input
Delta
CD#
Delta
RI#
Delta
DSR#
Delta
CTS#
1 1 1
SPR
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7] = 0
FCTR[6]=0
1 1 1
EMSR
WR
Rsvd
Rsvd
Auto
RTS
Hyst.
bit-3
Auto
RTS
Hyst.
bit-2
Rsvd
Rsvd
Rx/Tx
FIFO
Count
Rx/Tx
FIFO
Count
LCR[7] = 0
FCTR[6]=1
1 1 1
FLVL
RD
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
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