參數(shù)資料
型號(hào)： XRT16C854
廠商： Exar Corporation
英文描述： 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
中文描述： 2.97V至5.5V四路UART的128字節(jié)FIFO
文件頁(yè)數(shù)： 54/54頁(yè)
文件大?。?/td> 485K
代理商： XRT16C854
XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
xr
REV. 3.0.1
II
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION................................................................ 26
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 27
4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 27
4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... 27
T
ABLE
10: I
NTERRUPT
S
OURCE
AND
P
RIORITY
L
EVEL
..................................................................................................................... 28
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ...................................................................................... 28
T
ABLE
11: T
RANSMIT
AND
R
ECEIVE
FIFO T
RIGGER
L
EVEL
S
ELECTION
............................................................................................ 29
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ...................................................................................... 30
T
ABLE
12: P
ARITY
SELECTION
........................................................................................................................................................ 31
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 32
T
ABLE
13: INT O
UTPUT
M
ODES
..................................................................................................................................................... 32
4.8 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 33
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................... 34
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE .................................................................................... 35
4.11 ENHANCED MODE SELECT REGISTER (EMSR) ...................................................................................... 35
T
ABLE
14: S
CRATCHPAD
S
WAP
S
ELECTION
.................................................................................................................................... 35
T
ABLE
15: A
UTO
RTS H
YSTERESIS
............................................................................................................................................... 36
4.12 FIFO LEVEL REGISTER (FLVL) - READ-ONLY .......................................................................................... 36
4.13 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 36
4.14 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY .................................................................... 36
4.15 DEVICE REVISION REGISTER (DREV) - READ ONLY .............................................................................. 36
4.16 TRIGGER LEVEL (TRG) - WRITE-ONLY ..................................................................................................... 36
4.17 FIFO DATA COUNT REGISTER (FC) - READ-ONLY .................................................................................. 37
4.18 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE ........................................................................ 37
T
ABLE
16: T
RIGGER
T
ABLE
S
ELECT
................................................................................................................................................ 37
4.19 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE ........................................................................ 37
T
ABLE
17: S
OFTWARE
F
LOW
C
ONTROL
F
UNCTIONS
........................................................................................................................ 38
4.20 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE ................ 39
4.21 FIFO STATUS REGISTER (FSTAT) - READ/WRITE ................................................................................... 39
T
ABLE
18: UART RESET CONDITIONS FOR CHANNELS A-D.................................................................................................. 40
A
BSOLUTE
M
AXIMUM
R
ATINGS
......................................................................................................................41
T
YPICAL
P
ACKAGE
T
HERMAL
R
ESISTANCE
D
ATA
(M
ARGIN
OF
E
RROR
: = 15%) ..............................................41
DC E
LECTRICAL
C
HARACTERISTICS
..............................................................................................................41
TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc is 2.97 to 5.5V..................................................41
ELECTRICAL CHARACTERISTICS................................................................................41
AC E
LECTRICAL
C
HARACTERISTICS
..............................................................................................................42
TA=0
O
TO
70
O
C (-40
O
TO
+85
O
C
FOR
INDUSTRIAL
GRADE
PACKAGE
), V
CC
IS
2.97
TO
5.5V.........................42
F
IGURE
14. C
LOCK
T
IMING
............................................................................................................................................................. 43
F
IGURE
15. M
ODEM
I
NPUT
/O
UTPUT
T
IMING
F
OR
C
HANNELS
A-D .................................................................................................... 43
F
IGURE
17. 16 M
ODE
(I
NTEL
) D
ATA
B
US
W
RITE
T
IMING
FOR
C
HANNELS
A-D.................................................................................. 44
F
IGURE
16. 16 M
ODE
(I
NTEL
) D
ATA
B
US
R
EAD
T
IMING
FOR
C
HANNELS
A-D.................................................................................... 44
F
IGURE
18. 68 M
ODE
(M
OTOROLA
) D
ATA
B
US
R
EAD
T
IMING
FOR
C
HANNELS
A-D........................................................................... 45
F
IGURE
19. 68 M
ODE
(M
OTOROLA
) D
ATA
B
US
W
RITE
T
IMING
FOR
C
HANNELS
A-D ......................................................................... 45
F
IGURE
20. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[N
ON
-FIFO M
ODE
]
FOR
C
HANNELS
A-D ............................................................ 46
F
IGURE
21. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[N
ON
-FIFO M
ODE
]
FOR
C
HANNELS
A-D .......................................................... 46
F
IGURE
22. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA D
ISABLED
]
FOR
C
HANNELS
A-D........................................... 47
F
IGURE
23. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA E
NABLED
]
FOR
C
HANNELS
A-D............................................ 47
F
IGURE
24. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA M
ODE
D
ISABLED
]
FOR
C
HANNELS
A-D............................... 48
P
ACKAGE
D
IMENSIONS
.................................................................................................................................49
R
EVISION
H
ISTORY
.......................................................................................................................................52
T
ABLE
OF
C
ONTENTS
............................................................................................................
I
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