參數(shù)資料
型號(hào)： XRT16C854
廠商： Exar Corporation
英文描述： 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
中文描述： 2.97V至5.5V四路UART的128字節(jié)FIFO
文件頁(yè)數(shù)： 52/54頁(yè)
文件大?。?/td> 485K
代理商： XRT16C854
XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
xr
REV. 3.0.1
52
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2005 EXAR Corporation
Datasheet August 2005.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
REVISION HISTORY
D
ATE
R
EVISION
D
ESCRIPTION
November 1999
Rev 1.0
Removed Preliminary designation.
February 2002
Rev 2.0
Changed to standard style format. Text descriptions were clarified and sim-
plified (eg. DMA operation, FIFO mode vs. Non-FIFO mode operations etc).
Corrected RTS Hysteresis character values in
Table 15
. Clarified timing dia-
grams. Renamed Rclk (Receive Clock) to Bclk (Baud Clock) and timing
symbols. Added T
CS
, T
RWS
and T
RST
.
May 2003
Rev 2.1
Added patent number and updated Block Diagram.
June 2003
Rev 2.2
Added and updated device status in Ordering Information.
January 2004
Rev 3.0
Changed to standard style format. Clarified sleep mode conditions. Devices
with top mark date code of "F2 YYWW" and newer have 5V tolerant inputs
(except for XTAL1). Devices with top mark date code of "DC YYWW" and
older do not have 5V tolerant inputs.
August 2005
Rev 3.0.1
Updated the 1.4mm-thick Quad Flat Pack package description from "TQFP"
to "LQFP" to be consistent with the JEDEC and Industry norms.
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