參數(shù)資料
型號： XRT4500CV
廠商： EXAR CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP80
封裝： 14 X 14 MM, 1.40 MM HEIGHT, TQFP-80
文件頁數(shù)： 5/99頁
文件大?。?/td> 1384K
代理商： XRT4500CV
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
á
II
F
IGURE
22. I
LLUSTRATION
OF
A
“2-C
LOCK
DTE/DCE” I
NTERFACE
............................................................................51
F
IGURE
23. T
HE
B
EHAVIOR
OF
THE
TXC
AND
TXD S
IGNALS
AT
THE
DCE
AND
DTE SCC
S
, (D
ATA
R
ATE
= 1.0M
BPS
, “DCE-
TO
-DTE”
PROPAGATION
DELAY
= 160
NS
, “DTE-
TO
-DCE”
PROPAGATION
DELAY
= 160
NS
)............................52
F
IGURE
24. T
HE
B
EHAVIOR
OF
THE
TXC
AND
TXD S
IGNALS
AT
THE
DCE
AND
DTE SCC
S
(D
ATA
R
ATE
= 1.544M
BPS
, DCE-
TO
-DTE P
ROPAGATION
D
ELAY
= 160
NS
, DTE-
TO
-DCE P
ROPAGATION
D
ELAY
= 160
NS
) .............................52
F
IGURE
25. I
LLUSTRATION
OF
THE
“E
CHO
-C
LOCK
” F
EATURE
WITHIN
THE
XRT4500...................................................53
F
IGURE
26. I
LLUSTRATION
OF
THE
W
AVE
-
FORMS
,
ACROSS
A
DCE/DTE I
NTERFACE
,
WHEN
THE
E
CHO
-C
LOCK
F
EATURE
(
WITHIN
THE
XRT4500)
IS
USED
AS
DEPICTED
IN
F
IGURE
25........................................................................54
1.3.5 THE “2CK/3CK” (2-CLOCK/3-CLOCK MODE - ENABLE/DISABLE SELECT INPUT PIN)..................................... 54
F
IGURE
27. I
LLUSTRATION
OF
THE
DCE/DTE I
NTERFACE
,
WITH
THE
DCE M
ODE
XRT4500
OPERATING
IN
THE
“2-C
LOCK
”
M
ODE
........................................................................................................................................................55
1.3.6 THE “CLOCK INVERSION” (CK_INV) FEATURE..................................................................................................... 55
F
IGURE
28. I
LLUSTRATION
OF
THE
DCE M
ODE
XRT4500
BEING
CONFIGURED
TO
INVERT
THE
TXC
SIGNAL
................56
F
IGURE
29. I
LLUSTRATION
OF
THE
DTE M
ODE
XRT4500
BEING
CONFIGURED
TO
INVERT
THE
TXC
SIGNAL
................56
F
IGURE
30. I
LLUSTRATION
OF
THE
DCE M
ODE
XRT4500,
WHICH
IS
OPERATING
IN
THE
“2-C
LOCK
” M
ODE
,
AND
INVERTING
THE
“TXC”
SIGNAL
.....................................................................................................................................57
1.3.7 THE LATCH MODE OF OPERATION ........................................................................................................................ 58
1.3.8 THE REGISTERED MODE OF OPERATION ............................................................................................................. 58
F
IGURE
31. A
N
I
LLUSTRATION
OF
THE
E
FFECTIVE
I
NTERFACE
BETWEEN
THE
XRT4500
AND
THE
SCC/M
ICROPROCESSOR
WHEN
THE
“R
EGISTERED
” M
ODE
IS
ENABLED
...............................................................................................58
F
IGURE
32. A
N
I
LLUSTRATION
OF
THE
N
ECESSARY
G
LUE
L
OGIC
REQUIRED
TO
DESIGN
A
FEATURE
SIMILAR
TO
THAT
OFFERED
BY
THE
“R
EGISTERED
” M
ODE
,
WHEN
USING
A
DIFFERENT
M
ULTI
-
PROTOCOL
S
ERIAL
N
ETWORK
I
NTERFACE
IC59
1.3.9 THE INTERNAL OSCILLATOR .................................................................................................................................. 59
F
IGURE
33. I
LLUSTRATION
OF
THE
I
NTERNAL
O
SCILLATORS
WITHIN
THE
XRT4500.....................................................60
1.3.10 GLITCH FILTERS...................................................................................................................................................... 60
1.3.11 DATA INVERSION .................................................................................................................................................... 60
1.3.12 DATA INTERLUDE ................................................................................................................................................... 60
2.0 RECEIVER AND TRANSMITTER SPECIFICATIONS .........................................................................60
3.0 V.10\V.28 OUTPUT PULSE RISE AND FALL TIME CONTROL .........................................................60
F
IGURE
34. V.10 R
ISE
/F
ALL
T
IME
AS
A
F
UNCTION
OF
RSLEW .................................................................................61
F
IGURE
35. V.28 S
LEW
R
ATE
O
VER
± 3 V O
UTPUT
R
ANGE
WITH
3
K
W
IN
P
ARALLEL
WITH
2500
P
F L
OAD
AS
A
F
UNCTION
OF
RSLEW................................................................................................................................................61
4.0 THE HIGH-SPEED RS232 MODE ........................................................................................................61
5.0 INTERNAL CABLE TERMINATIONS ..................................................................................................62
6.0 OPERATIONAL SCENARIOS ..............................................................................................................62
7.0 APPLICATIONS INFORMATION .........................................................................................................62
F
IGURE
36. R
ECEIVER
T
ERMINATION
........................................................................................................................63
T
ABLE
6: R
ECEIVER
S
WITCHES
................................................................................................................................63
F
IGURE
37. T
RANSMITTER
T
ERMINATION
..................................................................................................................64
T
ABLE
7: T
RANSMITTER
S
WITCHES
...........................................................................................................................64
F
IGURE
38. T
YPICAL
V.10
OR
V.28 I
NTERFACE
(R1 = 10 KW
IN
V.10
AND
5 KW
IN
V.28)........................................64
F
IGURE
39. T
YPICAL
V.11 I
NTERFACE
(T
ERMINATION
R
ESISTOR
, R1,
IS
O
PTIONAL
.)..................................................64
F
IGURE
40. T
YPICAL
V.35 I
NTERFACE
......................................................................................................................65
T
ABLE
8: MUX1 C
ONNECTION
T
ABLE
.......................................................................................................................65
T
ABLE
9: MUX2 C
ONNECTION
T
ABLE
(RX4-RX7, TX4-TX7), O
UTPUT
V
ERSUS
I
NPUT
..............................................67
F
IGURE
41. S
CENARIO
A, MUX2, (DCE/DTE = 0, LP = 0).......................................................................................68
F
IGURE
42. S
CENARIO
B, MUX2, (DCE/DTE = 0, LP = 1), L
OOP
B
ACK
N
OT
ENABLED
.............................................69
F
IGURE
43. S
CENARIO
C, MUX2, (DCE/DTE = 1, LP = 0).......................................................................................70
F
IGURE
44. S
CENARIO
D, MUX2, (DCE/DTE = 1, LP = 1), L
OOP
B
ACK
N
OT
ENABLED
.............................................71
F
IGURE
45. S
ERIAL
I
NTERFACE
S
IGNALS
AND
C
ONNECTOR
P
IN
-O
UT
.........................................................................72
F
IGURE
46. S
ERIAL
I
NTERFACE
C
ONNECTOR
D
RAWINGS
...........................................................................................73
F
IGURE
47. EIA-530 C
ONNECTION
D
IAGRAM
FOR
XRT4500 ....................................................................................74
F
IGURE
48. RS-232 C
ONNECTION
D
IAGRAM
FOR
XRT4500 .....................................................................................75
Scenarios 1 & 2 Normal: ‘3-clock’ DCE/DTE Interface Operation...........................................................76
Input Pin Settings ....................................................................................................................................76
Scenario 3 &2 DTE Loop-Back Mode......................................................................................................77
Input Pin Settings ....................................................................................................................................77
Scenario 4 ...............................................................................................................................................78
Comments: DCE Loop-Back Mode .........................................................................................................78
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