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| 型號： | XRT4500CV |
| 廠商： | EXAR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | MULTIPROTOCOL SERIAL NETWORK INTERFACE IC |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP80 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-80 |
| 文件頁數(shù)： | 54/99頁 |
| 文件大小： | 1384K |
| 代理商： | XRT4500CV |
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á
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
51
Since the DTE SCC will not provide the DCE SCC
with the SCTE signal, the DCE SCC will have to use
a different clock signal in order to sample the “incom-
ing” data on the TXD line. A common approach, in
this case, is to simply “hard-wire” the “TXC” output
signal to the “SCTE” input pin of the DCE SCC) and
to use the falling edge of the TXC clock signal in order
to sample the “incoming” data on the TXD line, as il-
lustrated above in Figure 1.8.
N
OTE
:
There are numerous bad things about designing
DCE Equipment, per the illustration in Figure 1.9. In addi-
tion to the reasons presented below, since the DCE SCC is
now “hard-wired” to use the “TXC” as the means to sample
the “incoming” “TXD” signal, this approach is not flexible if
the user is interfacing to a DTE that happens to support “3-
Clock” signal. In this case, the user is advised to consider
using the “2-Clock” Mode feature (which is also offered by
the XRT4500) and is discussed in Section 1.2.5.
Important things to note about Figure 1.9.
1. The DTE SCC will not supply the SCTE signal to
the DCE SCC.
2. The DCE SCC will use the falling edge of the (lo-
cally generated) TXC clock signal in order to sample
the “incoming” TXD signal.
Unlike the “3-Clock DTE/DCE” Interface, the “2-Clock
DTE/DCE” Interface is sensitive to the “round-trip”
propagation delay between the DCE and the DTE
Terminals (due to the cable, components comprising
the DCE and DTE Terminals, etc.) An example of this
sensitivity is presented below.
Case 1 - “2-Clock DTE/DCE” Operation at
1.0Mbps
Consider the case where the DCE and DTE are ex-
changing data at a rate of 1.0Mbps. Further, let's con-
sider that the total propagation delay from the DCE to
the DTE is 160 ns. Likewise, let's consider that the to-
tal propagation delay from the DTE to the DCE is also
160ns. Given these conditions, Figure 23 plots out
the clock and signal wave-forms for the TXC and TXD
at both the DCE and DTE SCCs.
F
IGURE
22. I
LLUSTRATION
OF
A
“2-C
LOCK
DTE/DCE” I
NTERFACE
2
SCC (R)
SCC (L)
XRT4500
XRT4500
RX1
TX2
RXD
RXC
TXC
SCTE_IN
TXD_IN
TXD
SCTE
TXC_IN
RXC_IN
RXD_IN
60
67
73
74
1
78
79
77
76
70
71
64
65
63
62
1
74
68
67
60
63
62
64
65
70
71
77
76
78
79
TXD
TXC
RXC
RXD
DCE
DTE
TX1
RX3
RX2
RX1
RX2
TX3
TX2
TX1
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