參數(shù)資料
型號(hào)： XRT4500CV
廠商： EXAR CORP
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP80
封裝： 14 X 14 MM, 1.40 MM HEIGHT, TQFP-80
文件頁(yè)數(shù)： 57/99頁(yè)
文件大?。?/td> 1384K
代理商： XRT4500CV
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
á
54
By using the “Echo-Clock” feature, within the
XRT4500, the “Overall System” (comprised of the
DTE and DCE Terminals) is nearly as immune to the
“2-Clock/Propagation Delay” phenomenon, as is the
“3-Clock DTE/DCE Interface”; even though the DTE
SCC only processes two clock signals.
Hence, in short, the purpose of the Echo-Clock Mode
is to provide the “Overall-System” with the SCTE
clock signal, when it is not being supplied by the DTE
SCC. The impact of being able to accomplish this is a
more robust, reliable system performance.
Configuring the Echo-Clock Mode
The user can configure the “Echo-Clock” Mode, with-
in the XRT4500, by pulling the “EC” input pin (pin 34)
“l(fā)ow”. Conversely, the user can disable the “Echo-
Clock” Mode by pulling the “EC” input pin “high”.
When the “EC” input pin is pulled “l(fā)ow”, then the
XRT4500 will internally use the “TXC” digital signal
(which is output, from the DTE Mode XRT4500, via
the RX3D output pin) as the source for the “SCTE” (or
the TX2D) signal.
N
OTE
:
The “Echo-Clock” Mode is only available if the
XRT4500 is operating the DTE Mode.
1.3.5
The “2CK/3CK” (2-Clock/3-Clock Mode -
Enable/Disable Select Input pin)
Section 1.3.4 discusses the “Echo-Clock” Mode, and
how it can be used to combat the “2-Clock/Propaga-
tion Delay” phenomenon. The “Echo-Clock” Mode is
an approach that can be used to attack this phenom-
enon, if the XRT4500 is designed into a DTE Equip-
ment. However, if a system manufacturer, of DCE
Equipment, encounters this problem, one is not able
to configure a way out of this phenomenon by en-
abling the “Echo-Clock” Mode. Fortunately, the
XRT4500 does offer the “DCE Equipment” design a
couple of another options which can be used to miti-
gate the “2-Clock/Propagation Delay” phenomenon.
These two features are:
The “2-Clock/3-Clock Mode” Feature
The “Clock Inversion” Feature
This section discusses the “2-Clock/3-Clock” Feature.
As mentioned above, if the DTE/DCE Interface only
consists of two clock signals, (e.g., missing the SCTE
signal), then there will be some data rates at which
the DCE SCC will not be provided with sufficient set-
up time, when sampling the TXD signal.
Figure 27 presents an illustration of two XRT4500 be-
ing implemented in a “DTE/DCE” Interface. In this fig-
ure, the “DCE Mode” XRT4500 has been configured
to operate in the “2-Clock” Mode. When the XRT4500
is configured to operate in the “2-Clock” Mode, then it
will internally use the “TXC” signal as a means to syn-
thesize the “SCTE” clock signal (as depicted below).
F
IGURE
26. I
LLUSTRATION
OF
THE
W
AVE
-
FORMS
,
ACROSS
A
DCE/DTE I
NTERFACE
,
WHEN
THE
E
CHO
-C
LOCK
F
EATURE
(
WITHIN
THE
XRT4500)
IS
USED
AS
DEPICTED
IN
F
IGURE
25
TXC (at DCE)
TXC (at DTE)
TXD (at DTE)
TXD (at DCE)
0.5*tb
SCTE (at DTE)
SCTE (at DCE)
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